E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

10.3.2. Debug Parameters for Intel® Stratix® 10 E-Tile Transceiver Native PHY IP in the Parameter Editor

The following figure illustrates the parameters that you must enable to debug transceivers in Intel® Stratix® 10 E-Tile designs.
Figure 127. Parameters for Transceiver Debug in Intel® Stratix® 10 E-Tile Transceiver Native PHY IP
For more information about dynamic reconfiguration parameters refer to section Dynamic Reconfiguration.

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