E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.31. rsfec_corr_0s_cnt (High)

Register Name Description Address Addressing Mode
rsfec_corr_0s_cnt_0_hi RS-FEC number of bits corrected 0->1 for the lane (high word: bits 63 to 32) 0x264 32-bits
rsfec_corr_0s_cnt_1_hi 0x26C
rsfec_corr_0s_cnt_2_hi 0x274
rsfec_corr_0s_cnt_3_hi 0x27C
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
31:0 stat Statistics value.

RO

WO

-

0x0000 0000

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