E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

2.2.5.2. Gearbox 64/66

Because E-tile transceivers do not support 66 bit interface natively, you can use Gearbox 64/66 mode if the protocol design uses a 66 bit interface. You must use data_valid signals on both the TX and RX directions.

While configuring the transceiver Native PHY, you can specify parameters and modes from transceiver configuration rules given under Datapath Options in the Parameter Editor.

Table 24.  Gearbox 64/66 Interface Ports
Parameter Name Description
Enable tx_enh_pmaif_fifo_almost_full port Indicates when the TX PMA interface FIFO is almost full. This signal is transferred over a fast shift register (FSR).
Enable tx_enh_pmaif_fifo_almost_empty port Indicates when the TX PMA interface FIFO is almost empty. This signal is transferred over a slow` shift register (SSR).
Enable tx_enh_pmaif_fifo_overflow port Indicates when the TX PMA Interface FIFO has overflow. This signal is transferred over SSR.
Enable tx_enh_pmaif_fifo_underflow port Indicates when the TX PMA interface FIFO has underflow. This signal is transferred over SSR.
Enable RX PMA interface FIFO almost full threshold Indicates when the TX PMA interface FIFO is almost full. This signal is transferred over FSR.
Enable RX PMA interface FIFO almost empty threshold Indicates when the TX PMA interface FIFO is almost empty. This signal is transferred over SSR.
Enable rx_pmaif_fifo_underflow port Indicates when the RX PMA interface FIFO has underflow. This signal is transferred over FSR.
Enable rx_enh_pmaif_fifo_overflow port Indicates when the RX PMA interface FIFO has overflow. This signal is transferred over SSR.
Enable TX bit reversal 6 See the footnote.6
Enable RX bit reversal6 See the footnote.6
Enable TX sync header bit reversal6 See the footnote.6
Enable RX sync header bit reversal6 See the footnote.6
Enable tx_pmaif_bitslip port Gearbox TX bitslip control
Enable rx_pmaif_bitslip port Gearbox RX bitslip control. The rx_parallel_data slips 1 bit for every positive edge of the rx_pmaif_bitslip input. Keep the rx_pmaif_bitslip pulse high for at least 200 ns and each pulse 400 ns apart to ensure that the data is slipped. The maximum shift is <pcswidth - 1> bits. Therefore, if the PCS is 64 bits wide, you can shift 0-63 bits.
TX sync header location6 See the footnote.6
RX sync header location6 See the footnote.6

Restrictions:

  • There are restrictions on power saving simplex modes.
  • Configuring TX and RX data paths with different data rates is not supported.
  • There is no user-defined read enable on the RX PMAIF FIFO. It is only supported in Interlaken with the use of an internal .ini. For more details, contact My Intel support.
6 For 66 bit parallel data to be transmitted, data[65:64] is considered sync header bits and data[63:0] is considered as data bits. Bit reversals are applied to sync header and data bits separately. The sync header location parameter takes effect after bit reversals. If 1-0 is selected for the sync header location, the sync header is placed into LSB, in other words, the data is rearranged as {data[63:0], data[65:64]}. If 65-64 is selected for the sync header location, the data is left untouched. Parameters on RX work similarly.

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