E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.1.3. PMA Avalon® Memory-Mapped Interface

Table 78.  PMA Avalon® Memory-Mapped Interface
Address Bit Offset Description
0x4 [0] TX datapath clock enable
[1] Transmit full clock out (PMA Clock) enable
[4:2] Transmit data-input select, Default: 3'b000
[5] Transmit full clock out (clk_tx_adapt) select
[6] Transmit clock datapath select
[7] Transmit adaptation order select. Determines how 64 bits are sent to 32-bit transceiver channel
0x5 [1:0] Transmit multi-lane data select
[2] TX Gearbox clock enable
[3] TX datapath clock enable
[4] TX PCS div2 clock input enable
[5] TX FEC div2 clock input enable
[6] TX EHIP div2 clock input enable
[7] TX direct clock input enable
0x6 [0] RX datapath clock enable
[1] Receive full clock out (rx_pma_clk) enable
[2] Receive half clock out (rx_pcs_clk) enable
[3] Receive div66 clock out (rx_pcs_div66_clk) enable
[4] Receiver adaptation order select. Determines how 64 bits are combined from 32-bit transceiver channel
[6:5] Receiver adapter data select
[7] Receiver reverse bit order in Gearbox
0x7 [0] Receiver reverse 64/66 sync header bit order in Gearbox
[1] RX FIFO Read clock enable
[2] Receive Gearbox and FIFO write clock enable
[4:3] Receive direct-data mode multi-lane data select. Only active if cfg_rx_adapter_sel is not equal to b'01. These are one-hot encoded
[6:5] Select RX FIFO Read clock
[7] RX adapter clock enable
0x8 [0] Reverse data bit transmission order in TX Gearbox
[1] Reverse 64/66 sync header bit order transmission in TX Gearbox
[3] Dynamic bitslip enable for TX Gearbox
[5] Specify 64/66 sync header location in TX Gearbox
0x9 [1:0] TX Deskew multi-lane mode select
[3:2] TX deskew bits

00 = not yet received a deskew-bit

01 = not aligned

10 = received 1 set of aligned deskew-bits

11 = received 16 sets of aligned deskew-bits

[4] TX deskew alignment status

0 = not aligned or not enabled or didn't receive a deskew-bit

1 = aligned

[5] RX FIFO bit-67 select
0xA [2:0] Transmit deskew enable (using one-hot encoding)
[5] Dynamic rx_bitslip enable
0x10 [4:0] Transceiver interface RX FIFO empty threshold
[7:6] Transceiver interface RX FIFO almost empty threshold
0x11 [2:0] Transceiver interface RX FIFO almost empty threshold
[7:4] Transceiver interface RX FIFO full threshold
0x12 [0] Transceiver interface RX FIFO full threshold
[6:2] Transceiver interface RX FIFO almost full threshold
0x13 [6] RX FIFO Read when Empty
[7] RX FIFO Write when Full
0x14 [4:0] Transceiver interface TX FIFO empty threshold
[7:6] Transceiver interface TX FIFO almost empty threshold
0x15 [2:0] Transceiver interface TX FIFO almost empty threshold
[7:4] Transceiver interface TX FIFO full threshold
0x16 [0] Transceiver interface TX FIFO full threshold
[6:2] Transceiver interface TX FIFO almost full threshold
0x17 [5:4] TX FIFO Phase Compensation mode
[6] TX FIFO Write when Full
[7] TX FIFO Read when Empty
0x1C [7:0] Transmit output value [31:0] when the user_reset is active (after FPGA initialization)
0x1D [7:0] Transmit output value [31:0] when the user_reset is active (after FPGA initialization)
0x1E [7:0] Transmit output value [31:0] when the user_reset is active (after FPGA initialization)
0x1F [7:0] Transmit output value [31:0] when the user_reset is active (after FPGA initialization)
0x20 [7:0] Transmit output value [63:32] when the user_reset is active (after FPGA initialization)
0x21 [7:0] Transmit output value [63:32] when the user_reset is active (after FPGA initialization)
0x22 [7:0] Transmit output value [63:32] when the user_reset is active (after FPGA initialization)
0x23 [7:0] Transmit output value [63:32] when the user_reset is active (after FPGA initialization)
0x24 [2:0] Transmit output value [66:64] when the user_reset is active (after FPGA initialization)
0x28 [14:8] RX bit position for Async latency pulse generator (deterministic latency).
[6:0] Number of RX bitslip pulses received by the RX gearbox since the previous reset.
0x34 [1:0] Serialization factor for rx_bit_counter
[7:4] The value at which rx_bit_counter should reset to 0. Set to 5280-32 for RS-FEC
0x35 [7:0] The value at which rx_bit_counter should reset to 0. Set to 5280-32 for RS-FEC
0x36 [0] The value at which rx_bit_counter should reset to 0. Set to 5280-32 for RS-FEC
[3] Read-Write self clear
[4] transmit div66 clock out (tx_pcs_div66_clk) enable
0x37 [0] Transmit sclk_enable
[2:1] Increment TX FIFO latency select
[4] Receive sclk_enable
[6:5] Increment RX FIFO latency select
[7] Async latency pulse select
0x38 [0] Duty cycle correction: duty cycle correction bypass disable
[1] DCC: DCC master enable
[2] DCC: select continuous cal
0x3C [1] DCC : enable for FSM
0x80 [7:0] Core PMA attribute control
0x81 [7:0] Core PMA attribute control
0x84 [7:0] PMA attribute data
0x85 [7:0] PMA attribute data
0x86 [7:0] PMA attribute code
0x87 [7:0] PMA attribute code
0x88 [7:0] Lower byte of the PMA attribute code return value
0x89 [7:0] Upper byte of the PMA attribute code return value
0x8A [7] Indicates the PMA attribute has been transmitted to the PMA successfully
0x8B [0] 1'b0 indicates the PMA has finished acting on the PMA attribute and the PMA attribute code return value is available on registers 0x88/0x89
0x90 [0] Loads the contents of registers 0x84 to 0x87 (which form the PMA attribute contents) to the PMA
0x91 [0] Loads either the initial PMA setting or the last selected profile into the PMA. Used when changing the PMA's reference clock as described in Switching Reference Clocks.
0x95 [5] 1'b1 calibrates the PMA when loading new settings
0xEC [3:0] Selects reference clocks [0-8] muxed onto refclkin_in_A
[7:4] Selects which reference clock [0-8] is mapped to refclk4 in the Native PHY IP core
0xEE [3:0] Selects which reference clock [0-8] is mapped to refclk0 in the Native PHY IP core
[7:4] Selects which reference clock [0-8] is mapped to refclk1 in the Native PHY IP core
0xEF [3:0] Selects which reference clock [0-8] is mapped to refclk2 in the Native PHY IP core
[7:4] Selects which reference clock [0-8] is mapped to refclk3 in the Native PHY IP core
0x200 [7:0] Places the PMA in analog reset or sets up the PMA operating mode (see PMA Registers 0x200 to 0x203 Usage)
0x201 [7:0] Places the PMA in analog reset or sets up the PMA operating mode (see PMA Registers 0x200 to 0x203 Usage)
0x202 [7:0] Places the PMA in analog reset or sets up the PMA operating mode (see PMA Registers 0x200 to 0x203 Usage)
0x203 [7:0] Places the PMA in analog reset or sets up the PMA operating mode (see PMA Registers 0x200 to 0x203 Usage)
0x204 [7:0]

Returns the physical channel number in order to load the IP configuration to a different channel

0x207 [0]

0 indicates the operation completed successfully

0x207 [7] 1 indicates the last operation on registers 0x200 to 0x203 completed. You must also read 0x207[0] to check whether the operation was successful.

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