E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

2.2. Configuring the Native PHY IP Core

The E-tile transceiver Native PHY IP core is the primary design entry tool, and provides direct access to E-tile transceiver PHY features.
Use the Native PHY IP core in the Intel® Quartus® Prime Pro Edition software to configure the transceiver PHY for your protocol implementation. To instantiate the IP:
  1. Select the device family.
  2. Click Tools > IP Catalog to select the E-tile transceiver Native PHY IP core.
  3. Specify the IP parameters and configure the Native PHY IP core for your protocol implementation using the Parameter Editor.
  4. Use the Native PHY IP core to instantiate one of the following transceiver usage modes:
    • PMA Direct
    • PMA Direct high data rate PAM4

    Based on the transceiver configuration rule that you select, the Native PHY IP core guides you to configure the transceiver appropriately.

  5. After you configure the Native PHY IP core in the Parameter Editor, click Generate HDL to generate the IP instance.

    The top-level file generated with the IP instance includes all the available ports for your configuration. Use these ports to connect the Native PHY IP core to the clock network, the reset controller if you are not using Native PHY IP core's reset controller, and to other IP cores in your design.

    Figure 21. Native PHY IP Core Parameter Editor
    Note: Although the Intel® Quartus® Prime Pro Edition software provides legality checks, the supported FPGA fabric to transceiver interface widths and the supported data rates are pending characterization.

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