E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

7.7.2. Embedded Reconfiguration Streamer

You can optionally enable the embedded reconfiguration streamer in the Native PHY IP cores to automate the reconfiguration operation. The embedded reconfiguration streamer is a feature block that can perform Avalon® memory-mapped interface transactions to access channel configuration registers in the transceiver. When you enable the embedded streamer, the Native PHY IP cores embed HDL code for reconfiguration profile storage and reconfiguration control logic in the IP files.

If the new profile requires changing PMA attributes that can only be performed when the PMA is disabled, you need to do the following:

  1. Assert digital reset.
  2. Disable the PMA using PMA attribute code 0x0001.
  3. Set the PMA into analog reset.
  4. Write to Avalon® memory-mapped interface 0x40140 with the following bit pattern:
    • Bits [2:0] equal to the new profile
    • Bit [7] equal to 1 to launch the reconfiguration streamer

    The reconfiguration streaming automatically requests PMA recalibration.

  5. Continuously read register 0x40141[0]. It asserts high while loading the new profile and goes low after the new profile has finished loading. The PMA is now enabled and calibrated.
  6. Deassert digital reset.

If the new profile does not require the PMA to be disabled, you need to do the following:

  1. Write to Avalon® memory-mapped interface 0x40140 with the following bit pattern:
    • Bits [2:0] equal to the new profile
    • Bit [7] equal to 1 to launch the reconfiguration streamer
  2. Continue to read register 0x40141[0] until it becomes 0 to indicate that the reconfiguration streamer is finished.

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