6.7. Intel® Quartus® Prime Instantiated Transceiver Reset Sequencer
No intervention – The designer does not need to expose every reset request and acknowledge port on the interfaces of the design modules to be connected to the Master TRS.
Design modularity – Local changes to the number of transceiver reset signals at a lower hierarchy in a module does not require a chain of interface changes up to the Master TRS hierarchy, especially if the transceiver instance is deep down in the design hierarchy.
It is harder to debug a possible connectivity issue in Synthesis than debugging the RTL.
Any issue with the instantiation and connectivity needs to be fixed in Synthesis instead of in the design.
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