E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

7.7.1. Reconfiguration Files

The E-tile Transceiver Native PHY IP core optionally allows you to save the parameters you specify for the IP instances as configuration files. The configuration file stores addresses and data values for that specific IP instance. The configuration files are generated during IP generation. They are located in the <IP instance name>/altera_xcvr_native_s10_etile_181/synth/reconfig subfolder of the IP instance. The configuration data is available in the following formats:

  • SystemVerilog packages: <name>.sv
  • C Header files: <name>.h
  • Memory Initialization File (MIF): <name>.mif

Select one or more of the configuration file formats on the Dynamic Reconfiguration tab of the Transceiver Native PHY parameter editor to store the configuration data. The contents of the configuration files can be used to reconfigure from one transceiver configuration to another.

Reconfiguration files do not support going from non-RS-FEC mode to RS-FEC mode nor from RS-FEC mode to non-RS-FEC mode.

The generated MIF files do not contain the RS-FEC registers that need to be reconfigured.

SystemVerilog Configuration File

package altera_xcvr_rcfg_10_reconfig_parameters_CFG0;

localparam ram_depth = 21;
function [34:0] get_ram_data;
  input integer index;
  automatic reg [0:20][34:0] ram_data = {
    35'h0380706, // [34:16]-DPRIO address=0x038; [15:8]-bit mask=0x07; [2:2]-hssi_xcvr_cfg_rb_cont_cal=dcc_cont_cal_en(1'h1); [1:1]-hssi_xcvr_cfg_rb_dcc_en=dcc_mast_en(1'h1); [0:0]-hssi_xcvr_cfg_rb_dcc_byp=dcc_byp_dis(1'h0);
    35'h03C0202, // [34:16]-DPRIO address=0x03C; [15:8]-bit mask=0x02; [1:1]-hssi_xcvr_cfg_dcc_csr_en_fsm=dcc_en_fsm(1'h1);
    35'h0A4FF40, // [34:16]-DPRIO address=0x0A4; [15:8]-bit mask=0xFF; [7:0]-hssi_xcvr_int_seq3_tx_refclk_ratio=64(8'h40);
    35'h0A8FF40, // [34:16]-DPRIO address=0x0A8; [15:8]-bit mask=0xFF; [7:0]-hssi_xcvr_int_seq4_rx_refclk_ratio=64(8'h40);
    35'h21A8080, // [34:16]-DPRIO address=0x21A; [15:8]-bit mask=0x80; [7:7]-hssi_adapt_rx_word_mark=wm_en(1'h1);
    35'h2310400, // [34:16]-DPRIO address=0x231; [15:8]-bit mask=0x04; [2:2]-hssi_aibcr_tx_aib_dllstr_align_dy_ctlsel=aib_dllstr_al
Note: DPRIO refers to Avalon® memory-mapped interface addresses.

The SystemVerilog configuration files contain two parts. The first part consists of a data array of 35-bit hexadecimal values. The second part consists of parameter values. For the data array, each 35-bit hexadecimal value is associated with a comment that describes the various bit positions.

Table 69.  Mapping of SystemVerilog Configuration File Line
Bit Position Description
[34:16] The Avalon® memory-mapped interface address.
[15:8] The Avalon® memory-mapped interface bit mask. The bit mask exposes the bits that are configured in either the Transceiver Native PHY IP cores.
[7:0] Feature bit values.

For example, a value of 35'h002310400 represents an address of 0x00231 and a bit mask of 0x04. There is a feature located on bit 2 named hssi_aibcr_tx_aib_dllstr_align_dy_ctlsel, and it is set to aib_dllstr_al, which has the value of 0. The MIF file and C header file are set up similarly to the SystemVerilog package file. Multiple transceiver features may reside at the same address. Also, a single transceiver feature may span across multiple addresses.

You can generate multiple configurations (up to eight) of the transceiver Native PHY IP core. You can select any configuration as the default device configuration.

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