Visible to Intel only — GUID: fmw1536163524863
Ixiasoft
Visible to Intel only — GUID: fmw1536163524863
Ixiasoft
9.5.21. rsfec_core_ecc_hold
Description | Address | Addressing Mode |
---|---|---|
RS-FEC SRAM ECC status hold | 0x1D0 | 32-bits |
Bit | Name | Description | SW Access HW Access Protection |
Reset |
---|---|---|---|---|
15:8 | mbe | SRAM ECC uncorrectable error detected. Same bit ordering as for .sbe above. |
W1C WO1S - |
0x00 |
7:0 | sbe | SRAM ECC correctable (single bit) error detected. Should not become set. One bit per SRAM. Bits 0-3 covers the deskew buffers for physical lanes 0-3 (only used when RSFEC_CORE_CFG.frac = none). Bits 4-7 covers the data buffers for the RS decoding. When RSFEC_CORE_CFG.frac = frac4, these are used 1:1 for the physical lanes 0-3. |
W1C WO1S - |
0x00 |
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