E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

7.14.2.2. Control and Status Registers

Control and status registers are optional registers that memory map the status outputs from and control inputs to the Native PHY. The control and status registers are located on the PMA Avalon® memory-mapped interface from 0x40000 to 0x5FFFF.

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