E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

2.2.11. Port Information

Table 32.  Port Information
Port Name Direction Clock Domain Width Description
pll_refclk0 Input N/A 1 bit for each channel Reference clock for the transceiver.
reset Input Asynchronous 1 bit for each channel Reset signal for the transceiver.
rx_serial_data Input N/A 1 bit for each channel Positive signal for the receiver.
rx_serial_data_n Input N/A 1 bit for each channel Negative signal for the receiver.
tx_serial_data Output N/A 1 bit for each channel Positive signal for the transmitter.
tx_serial_data_n Output N/A 1 bit for each channel Negative signal for the transmitter.
rx_parallel_data Output rx_coreclkin 80 bits for each channel Parallel data of the receiver side. Refer to Parallel Data.
tx_parallel_data Input tx_coreclkin 80 bits for each channel Parallel data of the transmitter side. Refer to Parallel Data.
tx_pma_ready Output tx_coreclkin 1 bit for each channel Ready status signal of the transmitter PMA.
tx_ready Output tx_coreclkin 1 bit for each channel Ready status signal of the transmitter.
rx_dskw_ready Output rx_coreclkin 1 bit for each PMA channel Ready status signal indicating that the deskew calculations are done and the data is available.
rx_pma_ready Output rx_coreclkin 1 bit for each channel Ready status signal of the receiver PMA.
rx_ready Output rx_coreclkin 1 bit for each channel Ready status signal of the receiver.
rx_is_lockedtodata Output Asynchronous 1 bit for each channel Locked to data status signal of the receiver.
rx_pma_elecidle Output Asynchronous 1 bit for each channel Electrical idle status signal of the receiver PMA.
rx_fifo_empty Output rx_coreclkin 1 bit for each channel When asserted, indicates that the RX core FIFO is empty. Because the FIFO depth is always constant when the FIFO is in phase compensation mode, you can ignore this signal when the FIFO is in phase compensation mode.
rx_fifo_full Output rx_coreclkin 1 bit for each channel When asserted, indicates that the RX core FIFO is full. Because the FIFO depth is always constant when the FIFO is in phase compensation mode, you can ignore this signal when the FIFO is in phase compensation mode.
rx_fifo_pempty Output rx_coreclkin 1 bit for each channel When asserted, indicates that the RX core FIFO is partially empty. Because the FIFO depth is always constant when the FIFO is in phase compensation mode, you can ignore this signal when the FIFO is in phase compensation mode.
rx_fifo_pfull Output rx_coreclkin 1 bit for each channel When asserted, indicates that the RX core FIFO is partially full. Because the FIFO depth is always constant when the FIFO is in phase compensation mode, you can ignore this signal when the FIFO is in phase compensation mode.
rx_fifo_rd_en Input rx_coreclkin 1 bit for each channel This port is used for Elastic FIFO mode. Asserting this signal enables the read from RX core FIFO.
tx_dll_lock Output tx_coreclkin 1 bit for each channel TX DLL locked status signal for data transfer.
tx_fifo_empty Output tx_coreclkin 1 bit for each channel When asserted, indicates that the TX core FIFO is empty. Because the FIFO depth is always constant when the FIFO is in phase compensation mode, you can ignore this signal when the FIFO is in phase compensation mode.
tx_fifo_full Output tx_coreclkin 1 bit for each channel When asserted, indicates that the TX core FIFO is full. Because the FIFO depth is always constant when the FIFO is in phase compensation mode, you can ignore this signal when the FIFO is in phase compensation mode.
tx_fifo_pempty Output tx_coreclkin 1 bit for each channel When asserted, indicates that the TX core FIFO is partially empty. Because the FIFO depth is always constant when the FIFO is in phase compensation mode, you can ignore this signal when the FIFO is in phase compensation mode.
tx_fifo_pfull Output tx_coreclkin 1 bit for each channel When asserted, indicates that the TX core FIFO is partially full. Because the FIFO depth is always constant when the FIFO is in phase compensation mode, you can ignore this signal when the FIFO is in phase compensation mode.
latency_sclk Input N/A 1 bit for each channel Reserved port. Do not connect.
rx_dl_async_pulse Output latency_sclk 1 bit for each channel Reserved port. Do not connect.
rx_dl_measure_sel Input latency_sclk 1 bit for each channel Reserved port. Do not connect.
tx_dl_async_pulse Output latency_sclk 1 bit for each channel Reserved port. Do not connect.
tx_dl_measure_sel Input latency_sclk 1 bit for each channel Reserved port. Do not connect.
tx_clkout Output N/A 1 bit for each channel Clock output from the transmitter. You can select the full-rate, half-rate, or div66 option in the Native PHY GUI.
tx_clkout2 Output N/A 1 bit for each channel Second clock output from the transmitter. You can select the full-rate, half-rate, or div66 option in the Native PHY GUI when the port is enabled.
tx_coreclkin Input N/A 1 bit for each channel Transfer clock between the FPGA core and the transmitter.
tx_coreclkin2 Input N/A 1 bit for each channel Second transfer clock between the FPGA core and the transmitter.
rx_clkout Output N/A 1 bit for each channel Clock output from the receiver. You can select the full-rate, half-rate, or div66 option in the Native PHY GUI.
rx_clkout2 Output N/A 1 bit for each channel Second clock output from the receiver. You can select the full-rate, half-rate, or div66 option in the Native PHY GUI when the port is enabled.
rx_coreclkin Input N/A 1 bit for each channel Transfer clock between the FPGA core and the receiver.
rsfec_avmm2_avmmread_in Input reconfig_rsfec_clk 1 bit Avalon® memory-mapped interface read signal of the Avalon® memory-mapped interface 2 for FEC.
rsfec_avmm2_avmmrequest_in Input reconfig_rsfec_clk 1 bit Avalon® memory-mapped interface request signal of the Avalon® memory-mapped interface 2 for FEC.
rsfec_avmm2_avmmwrite_in Input reconfig_rsfec_clk 1 bit Avalon® memory-mapped interface write signal of the Avalon® memory-mapped interface 2 for FEC.
rsfec_signal_ok[0] Input Asynchronous 1 bit for each channel Indicator to RS-FEC per lane that the PMA lane is up and stable8.

This signal may be tied to the rx_is_locked_to_data output for the corresponding transceiver lane.

rsfec_signal_ok[1] Input Asynchronous 1 bit for each channel
rsfec_signal_ok[2] Input Asynchronous 1 bit for each channel
rsfec_signal_ok[3] Input Asynchronous 1 bit for each channel
i_rsfec_pld_ready Input reconfig_rsfec_clk 1 bit Indicator to RS-FEC that the FPGA core and application layer is ready to start sending and receiving traffic.

This signal is normally tied to 1'b1. It may be driven from your design in special cases where the RS-FEC block needs to be enabled based on some other signal or signals in the design.

o_rsfec_channel_ssr[lane_no * 8 + 0] Output Asynchronous 1 bit per lane rsfec_lane_rx_stat.not_locked is an indicator of a not-locked signal status from rsfec_core. It is set when the core is not locked to alignment or codeword markers (100GbE/128 GFC/25GbE) or to FEC codewords (32 GFC).
o_rsfec_channel_ssr[lane_no * 8 + 1] Output Asynchronous 1 bit per lane rsfec_lane_rx_stat.hi_ser is an indicator of a high error rate from rsfec_core. It is set when the number of symbol errors in a block of 8,192 consecutive codewords has exceeded 417.
o_rsfec_channel_ssr[lane_no * 8 + 2] Output Asynchronous 1 bit per lane o_pcs_rx_sf is an indicator of a signal failure from rsfec_core.
o_rsfec_channel_ssr[lane_no * 8 + 3: lane_no * 8 + 7] Output Asynchronous 5 bits per lane Reserved port. Do not connect.
rsfec_usr_avmm2_rst Input Asynchronous 1 bit Indicator of an RS-FEC reconfiguration reset. Assert then deassert this signal before your design begins to process data. Assert this signal for a minimum of 250 ns.
rsfec_o_config_done Output Asynchronous 1 bit Indicator that the RS-FEC initial configuration is complete.
rsfec_o_fec_ready Output Asynchronous 1 bit Indicator that the RS-FEC is ready to accept transmit data.
rsfec_o_internal_error Output Asynchronous 1 bit Indicator of an internal error possibly due to an Avalon® memory-mapped interface access timeout.
rsfec_o_status_rx_not_align Output Asynchronous 1 bit Indicator that the incoming signal failed, the RX lanes are not all locked, alignment markers are not unique, or the skew is too large. Only applicable in multi-lane.
rsfec_o_status_rx_not_deskew Output Asynchronous 1 bit Indicator that all RX lanes are locked but the alignment markers were not unique or the skew was too large. Only applicable in multi-lane.
rsfec_o_tx_dsk_valid Output Asynchronous 1 bit Indicator of a successful deskew, only used for multi-lane RS-FEC direct mode.
reconfig_clk Input N/A 1 bit Clock signal of reconfiguration interface.
reconfig_reset Input reconfig_clk 1 bit Reset signal of reconfiguration interface.
reconfig_write Input reconfig_clk 1 bit Write signal of reconfiguration interface.
reconfig_read Input reconfig_clk 1 bit Read signal of reconfiguration interface.
reconfig_address Input reconfig_clk 19 bit Address signal of reconfiguration interface (the upper [n-1:19] address bits of the reconfiguration address bus specify the selected channel, where 'n' is the log base 2 of the number of channels).
reconfig_writedata Input reconfig_clk 8 bit Write data of reconfiguration interface.
reconfig_readdata Output reconfig_clk 8 bit Read data of reconfiguration interface.
reconfig_waitrequest Output reconfig_clk 1 bit Wait Request signal of reconfiguration interface.
Table 33.  Parallel Data
E-Tile Native PHY Mode TX/RX PMA Interface Width Enable TX/RX double width transfer Valid Parallel Data Note
PMA Direct 16 No Data [15:0] N/A
PMA Direct 20 No Data [19:0] N/A
PMA Direct 32 No Data [31:0] N/A
PMA Direct 40 No Data [39:0] N/A
PMA Direct 16 Yes

Data [55:40]

Data [15:0]

Data [55:40] is the first data group. Data [15:0] is the second data group.
PMA Direct 20 Yes

Data [59:40]

Data [19:0]

Data [59:40] is the first data group. Data [19:0] is the second data group.
PMA Direct 32 Yes

Data [71:40]

Data [31:0]

Data [71:40] is the first data group. Data [31:0] is the second data group.
PMA Direct high data rate PAM4 64 No

Data [111:80]

Data [31:0]

Data [31:0] is the lower bits data. Data [111:80] is the upper bits data.
PMA Direct high data rate PAM4 64 Yes

Data [151:120]

Data [71:40]

Data [111:80]

Data [31:0]

Data [111:80] and Data [31:0] are the first data group. In this group, Data [31:0] is the lower bits data. Data [111:80] is the upper bits data.

Data [151:120] and Data [71:40] are the second data group. In this group, Data [71:40] is the lower bits data. Data [151:120] is the upper bits data.

Bit Mapping for Native PHY TX and RX Datapaths

When the RS-FEC is enabled in the Native PHY IP, it is instantiated in the Native PHY IP netlist, and certain interface restrictions are required. In particular, the EMIB adapter FIFOs must be set to double-width mode, which means the TX and RX parallel datapaths are both 80 bits wide.

Also, it is necessary to clock the input side of the TX FIFO (80 bits wide) and the output side of the RX FIFO (80 bits wide) with a half-rate clock.

Because of the double-width Native PHY IP datapath interface, a mapping is required from the datapath ports accessible in the Native PHY IP core to the datapath. The mapping is shown in the table below.

Table 34.  80 Bit Data Native PHY IP Double-width TX/RX Ports
Bits 9 tx_parallel_data rx_parallel_data
79 word_marking_bit_msb word_marking_bit_msb
78 DESKEW DESKEW
77 SNAPSHOT RX_FIFO_USED[4:0]
76
75
74
73
72 RX_FIFO_EMPTY
71 RX_FIFO_PFULL
70
69 SYNC SYNC
68 VALID VALID
67
[66:40] TXDATA[65:39] RXDATA[65:39]
39 word_marking_bit_lsb word_marking_bit_lsb
[38:0] TXDATA[38:0] RXDATA[38:0]

The word marking bits are inserted automatically by the IP, so you do not need to do anything with these bits. You just need to map your data to the Native PHY IP TX and RX ports as shown.

Legend for the above table:

  • DESKEW: Deskew marker for each lane (When RS-FEC aggregate mode is enabled, the deskew bit of each channel on TX must be driven simultaneously with a pulse that repeats every 32 cycles of the parallel clock; RS-FEC drives deskew on RX automatically.)
  • RX_FIFO_EMPTY: RX FIFO empty status from the PMA interface
  • RX_FIFO_PFULL: RX FIFO partially full status from the PMA interface
  • SYNC (TX and RX): Data to PCS synchronization (alignment/codeword marker or 257b synchronization)
  • VALID:
    • TX: Deassert the valid line once every 33 cycles
    • RX: Data received from RS-FEC valid
  • RX_FIFO_USED[4:0]:
    • [0]: PMA interface TX FIFO almost empty
    • [1]: PMA interface TX FIFO partially full
    • [2]: PMA interface TX FIFO underflow
    • [3]: PMA interface TX FIFO overflow
    • [4]: PMA interface RX FIFO overflow
  • SNAPSHOT: Snapshot of the register counters. The rising edge of this signal latches running 64-bit counters into 32-bit registers. When 0, the registers are constantly being updated.
8 In PMA direct high data rate PAM4 mode, when 2x is selected for the number of channels, on the transceiver side, only even indexed channels are actively sending and receiving data; odd indexed channels are powered down and not usable for other purposes. Nevertheless, you must assert rsfec_signal_ok for all 2x even and odd indexed channels.
9 When the transcoder is bypassed, the 7 lsb bits [6:0] are set to zeros for TX. RX bit[6] is set to one if it is part of an uncorrectable FEC code word on RX and the remaining RX bits [5:0] are reserved.

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