E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.8. rsfec_debug_cfg

Description Address Addressing Mode
Extra config/debug on fec_clock 0x108 32-bits
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
31 main_rst

Main Soft Reset

Setting this bit causes main soft reset of RS-FEC including tx/rx path

RW

RO

-

0x0
29 rx_rst

RX Soft Reset

Setting this bit causes soft reset of the RX datapath in RS-FEC Core

RW

RO

-

0x0
28 tx_rst

TX Soft Reset

Setting this bit causes soft reset of the TX datapath in RS-FEC Core

RW

RO

-

0x0
7:4 shadow_clear

Clear Rsfec Counters

1: Clear the collection and shadow counters so that the next shadow request or snapshot starts from 0.

If the counters are not cleared, they continue counting and rollover.

RW

RO

-

0x0
3:0 shadow_req Shadow request.

Setting each bit freezes RS-FEC statistics register values of the lane and avoids a value change while reading the register. There is one bit per lane (bit0 = lane0).

RW

RO

-

0x0

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