E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.10. rsfec_lane_tx_hold

Register Name Description Address Addressing Mode
rsfec_lane_tx_hold_0 RS-FEC per lane TX status hold 0x130 32-bits
rsfec_lane_tx_hold_1 0x134
rsfec_lane_tx_hold_2 0x138
rsfec_lane_tx_hold_3 0x13C
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
3 pace_inv

PCS TX pacing violation.

With RS528 .pace_inv is never set.

With RS544 .pace_inv is set when the layer above presents TX data in more than 33 consecutive cycles.

W1C

W1S

-

0x0
2 resync

PCS Tx alignment/codeword marker resync.

Not valid when RSFEC_LANE_CFG1.eng_cust_am_en = 1.

W1C

W1S

-

0x0
1 blk_inv

PCS Tx 66b invalid block type.

Not valid when transcoding is bypassed.

W1C

W1S

-

0x0
0 hdr_inv

PCS Tx 66b invalid sync header.

Not valid when transcoding is bypassed.

W1C

W1S

-

0x0

Did you find the information on this page useful?

Characters remaining:

Feedback Message