E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

2.2.4.1. Core Interface Parameters

The core interface is the interface between the transceiver EMIB and the FPGA core EMIB. You can use these options to customize the core interface.

Based on the transceiver configuration rule you select, the Native PHY IP core Parameter Editor reports error or warning messages if your settings violate the protocol standard.

Table 19.  Core Interface Parameters
Parameter Range Description
General Core Interface Options
Enable TX fast pipeline registers On/Off Enables the optional fast pipeline registers in the TX parallel datapath. The fast pipeline registers are hyper-registers, which are clocked by the tx_coreclkin input. You must clear fast pipeline registers synchronously. Enable this option to achieve better setup time for TX parallel data transfer from the FPGA core to the transceiver.
Enable RX fast pipeline registers On/Off Enables the optional fast pipeline registers in the RX parallel datapath. The fast pipeline registers are hyper-registers, which are clocked by the rx_coreclkin input. You must clear fast pipeline registers synchronously. Enable this option to achieve better setup time for RX parallel data transfer from the transceiver to the FPGA core.
TX Core Interface FIFO
Enable TX double width transfer On/Off Enables or disables the TX transfer interface FIFO double width mode. Use this option when you need to divide the core frequency by two so as not to exceed the maximum EMIB frequency specifications. In duplex mode, select this parameter for both TX and RX simultaneously.
RX Core Interface FIFO
Enable RX double width transfer On/Off Enables or disables the RX transfer interface FIFO double width mode. Use this option when you need to divide the core frequency by two so as not to exceed the maximum EMIB frequency specifications. In duplex mode, select this parameter for both TX and RX simultaneously.

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