E-Tile Transceiver PHY User Guide

ID 683723
Date 4/01/2024
Document Table of Contents

4.2.7. PMA Direct 100GE PAM4 (50 Gbps x 2) (Aggregate FEC On)

The figure below shows the clocking scheme for two channels out of four being used in a 100GE PAM4 (50 Gbps x 2) scheme. The FEC clock across all four channels is shared and driven by the master channel. For Core Interface FIFOs in Phase Compensation mode, connect half-rate tx_clkout (415.0390625 MHz) to tx_coreclkin and rx_coreclkin. If you use any other source for tx_coreclkin, make sure tx_coreclkin has 0 PPM difference with tx_clkout.

Figure 72. PMA Direct 100GE PAM4 (50 Gbps x 2) (Aggregate FEC On)