E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

6.5.2. Manual Reset Mode

In manual mode, all ports are exposed to provide flexible control. Follow the reset sequence for RX and TX modes to send reset requests.

Note: The manual reset mode is required if fractured RS-FEC is used.
Table 63.  Native PHY IP Ports With Manual Mode Enabled
Port Direction Clock Domain Description
rx_reset_req Input Asynchronous Request to Master TRS to schedule RX reset
rx_reset_ack Output Asynchronous Valid window for you to assert/deassert rx_aib_reset, rx_pmaif_reset, rx_rsfec_reset
rx_aib_reset Input Asynchronous Reset RX EMIB datapath
rx_pmaif_reset Input Asynchronous Reset RX PMA digital logic
rx_rsfec_reset Input Asynchronous Reset RX RS-FEC datapath
rx_transfer_ready Output Asynchronous Output from the Native PHY IP core indicating the RX EMIB datapath is ready
rx_pma_ready Output Asynchronous Output from the PMA indicating the PMA is ready. This must be asserted before asserting or deasserting any RX resets.
rx_is_lockedtodata Output Asynchronous Output from the PMA indicating the CDR has locked to the incoming serial data
tx_reset_req Input Asynchronous Request to Master TRS to schedule TX reset
tx_reset_ack Output Asynchronous Valid window to assert or deassert tx_aib_reset, tx_pmaif_reset, tx_rsfec_reset, rsfec_reset
rsfec_reset Input Asynchronous Reset all RS-FEC logic
tx_aib_reset Input Asynchronous Reset TX EMIB datapath
tx_pmaif_reset Input Asynchronous Reset TX PMA digital logic
tx_rsfec_reset Input Asynchronous Reset TX RS-FEC datapath
tx_transfer_ready Output Asynchronous Output from the Native PHY IP core indicating the TX EMIB datapath is ready
tx_pma_ready Output Asynchronous Output from the PMA indicating the PMA is ready. This must be asserted before asserting or deasserting any TX resets.

The reset, rx_ready, and tx_ready ports do not appear in manual reset mode.

Figure 82. Manual Reset Mode

You assert the tx_reset_req or rx_reset_req ports to start the digital reset process. You need to assert tx_reset_req or rx_reset_req every time you want to assert or deassert reset signals. You can assert req ports on multiple channels at the same time. The Local TRS and Master TRS round robin and stagger the resets. However:

  • If you use the RS-FEC block and want to reset both the TX and RX, you must complete the TX reset on a specific channel before resetting the RX on that channel.
  • You must ensure that the tx_pma_ready output is asserted before asserting the tx_reset_req.
  • You must ensure that the rx_pma_ready output is asserted before asserting the rx_reset_req.
  • You must monitor rx_is_lockedtodata.
  • After rx_lockedtodata stays high for 180 µs, you may deassert the RX digital resets.

The following use model is supported:

  1. You assert multiple reset_req. The Local TRS forwards the reset_req signal to the Master TRS.
  2. The Master TRS selects one of the reset_req and waits 200 ns before asserting the reset_ack output.
  3. You assert the resets on the EMIB, RS-FEC, and PMA interfaces. See RX Reset Assertion Timing Waveform through TX PMA Reconfiguration with Reset Controller in Manual Mode Timing Waveform for TX and RX reset sequences.
  4. You deassert the reset_req signal after resetting the blocks.
  5. The Master TRS sees the deasserted reset_req and deasserts the reset_ack output.
    Note: The Master TRS automatically deasserts the reset_ack output after 400 µs if you have not deasserted the reset_req input. In that case, you must deassert and reassert the reset_req input to enter the round robin pool again.
  6. The Master TRS goes to the next request in a round robin fashion and waits 200 ns before asserting the next reset_ack.

The figure below shows how to use the tx_reset_req/rx_reset_req inputs to request a reset window and how tx_reset_ack/rx_reset_ack marks the Master TRS returning a valid reset window.

Figure 83. Manual Mode Reset Timing ModelDuring the timing window when the reset_ack output is high, reset the blocks in sequence. The numbers refer to the steps above.

RX Reset Assertion Timing Waveform and TX Reset Assertion Timing Waveform below show how to assert TX and RX reset.

Figure 84. RX Reset Assertion Timing Waveform
Figure 85. TX Reset Assertion Timing Waveform

RX Reset Deassertion Timing Waveform (PMA Direct Mode), RX Reset Deassertion Timing Waveform (RS-FEC Enabled) and TX Reset Deassertion Timing Waveform below show how to deassert TX and RX reset.

Figure 86. RX Reset Deassertion Timing Waveform (PMA Direct Mode)
Figure 87. RX Reset Deassertion Timing Waveform (RS-FEC Enabled)
Figure 88. TX Reset Deassertion Timing Waveform

Because you only have 400 μs to complete a reset sequence, there is not enough time to assert the reset, reconfigure the PMA, and deassert the reset. So you should assert the reset in one reset window, reconfigure the PMA, and then deassert the reset in a second window. Refer to RX PMA Reconfiguration with Reset Controller in Manual Mode Timing Waveform (PMA Direct Mode), RX PMA Reconfiguration with Reset Controller in Manual Mode Timing Waveform (RS-FEC Enabled) and TX PMA Reconfiguration with Reset Controller in Manual Mode Timing Waveform below for details.

The RS-FEC block automatically locks onto the FEC symbols and you do not need to reset the RS-FEC block through the rsfec_reset, tx_rsfec_reset, or rx_rsfec_reset signals.

Figure 89. RX PMA Reconfiguration with Reset Controller in Manual Mode Timing Waveform (PMA Direct Mode)
Figure 90. RX PMA Reconfiguration with Reset Controller in Manual Mode Timing Waveform (RS-FEC Enabled)
Figure 91. TX PMA Reconfiguration with Reset Controller in Manual Mode Timing Waveform

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