E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

8.2. PRBS Usage Model

The PRBS usage model is comprised of the PRBS pattern generator and verifier configuration and the hard PRBS error counter configuration. You can use PMA Direct Mode to implement PRBS (10G/25G) channels.

Different PRBS patterns can be configured using the 0x84, 0x85, 0x86, and 0x87 Avalon® memory-mapped interface addresses. The 0x84 and 0x85 Avalon® memory-mapped interface addresses point to the PRBS pattern code. The 0x86 and 0x87 Avalon® memory-mapped interface addresses point to the PMA code address 0x02.

Figure 111. Setting PMA Attributes for PRBS Through Avalon® Memory-Mapped Interface
Table 73.  PRBS Control PMA Attribute Code Definition, PMA Attribute Code 0x02, PRBS Enable
Address Direction Definition
0x84[2:0] input

3'b000: prbs7

3'b001: prbs9

3'b010: prbs11

3'b011: prbs15

3'b100: prbs23

3'b101: prbs31

3'b110: prbs13

3'b111: user

0x84[4] input Reseed on error
0x84[5] input Autoseed correct (generator goes from all ‘0’ to all ‘1’ if it occurs)
0x84[7] input Stop on error (RX)
0x85[0] input Load TX PRBSGEN
0x85[1] input Load RX PRBSGEN
Table 74.  PRBS Control PMA Attribute Code Definition, PMA Attribute Code 0x02, PRBS Disable
Address Direction Definition
0x85[7:0] 0x84[7:0] input

Disable codes

0x3ff: disable both generators

0x1ff: disable TX PRBSGEN

0x2ff: disable RX PRBSGEN

0x89[7:0] 0x88[7:0] return value

0x00: Failed due to background processes needing time to complete operations that may change the requested configuration. Wait some time and re-issue the request.

0x02: Success

For example, to use the PRBS31 generator and checker, do the following steps:

  1. Set TX PRBS31.
    1. Write 0x84[7:0] = 0x25.
    2. Write 0x85[7:0] = 0x01.
    3. Write 0x86[7:0] = 0x02.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  2. Set RX PRBS31.
    1. Write 0x84[7:0] = 0x35.
    2. Write 0x85[7:0] = 0x02.
    3. Write 0x86[7:0] = 0x02.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  3. Enable the transceiver channel if it is not running already.
    1. Write 0x84[7:0] = 0x07.
    2. Write 0x85[7:0] = 0x00.
    3. Write 0x86[7:0] = 0x01.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  4. Wait for tx_ready and rx_ready to both be 1.
  5. Set the data comparator.
    1. Write 0x84[7:0] = 0x03.
    2. Write 0x85[7:0] = 0x02.
    3. Write 0x86[7:0] = 0x03.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  6. Reset error counters.
    1. Write 0x84[7:0] = 0x00.
    2. Write 0x85[7:0] = 0x00.
    3. Write 0x86[7:0] = 0x17.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  7. Wait for the 32 bits wide error counter to be accumulated.
  8. Set the error count to be read out.
    1. Write 0x84[7:0] = 0x03.
    2. Write 0x85[7:0] = 0x00.
    3. Write 0x86[7:0] = 0x18.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  9. Read the lower 16 bits of the error counter.
    1. Write 0x84[7:0] = 0x00.
    2. Write 0x85[7:0] = 0x00.
    3. Write 0x86[7:0] = 0x1A.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
    9. Read 0x88[7:0]. This represents bits [7:0] of the error counter.
    10. Read 0x89[7:0]. This represents bits [15:8] of the error counter.
  10. Read the upper 16 bits of the error counter.
    1. Write 0x84[7:0] = 0x00.
    2. Write 0x85[7:0] = 0x00.
    3. Write 0x86[7:0] = 0x1a.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
    9. Read 0x88[7:0]. This represents bits [23:16] of the error counter.
    10. Read 0x89[7:0]. This represents bits [31:24] of the error counter.
Note: During PMA performance verification testing, with continuous adaptation running in background, error bits cannot be accumulated to calculate BER because the Hard PRBS error counter is in a busy state. You can read errors during continuous adaptation by implementing a soft PRBS generator and verifier. Errors can be accumulated in hard PRBS error counter after stopping the continuous adaptation.

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