E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

3.1.2.4. Deserializer

The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock, and deserializes the data using the low-speed parallel recovered clock. The deserializer forwards the deserialized data to the receiver PCS or FPGA core.

The channel deserializer supports the following deserialization factors: 16, 20, 32, 40, and 64.

Figure 51. DeserializerThe deserializer block sends out the LSB of the input data first.

Did you find the information on this page useful?

Characters remaining:

Feedback Message