E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

7.7.2.1. Register 0x40140

The Avalon® memory-mapped interface waitrequest signal does not assert when writing to the register to start the MIF streaming because the register is located in the FPGA core.

Figure 102. Loading MIF Profile 1 by Writing to Register 0x40140

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