E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.15. rsfec_lanes_rx_stat

Description Address Addressing Mode
RS-FEC combined lanes RX status 0x180 32-bits
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
1 not_deskew

All RX lanes locked but the alignment markers were not unique or the skew was too large.

This is an event signal, so use .not_align above instead to determine the alignment state.

Restarts the synchronization.

Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).

RO

WO

-

0x0
0 not_align

RX lanes not aligned (state).

Incoming signal fail, RX lanes not all locked, alignment markers not unique or skew too large.

Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).

RO

WO

-

0x0

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