E-Tile Transceiver PHY User Guide

ID 683723
Date 4/01/2024
Document Table of Contents

7.8. Arbitration

Figure 103. Arbitration
The arbitration logic allows multiple masters to control the Avalon® memory-mapped interface bus. The following feature blocks can access the programmable registers:
  • Embedded reconfiguration streamer
  • User reconfiguration logic connected to the reconfiguration interface

These feature blocks arbitrate for control over the programmable space of each transceiver channel. Each of these feature blocks can request access to the programmable registers of a channel by performing a read or write operation to that channel. For any of these feature blocks to be used, you must first have control over the internal configuration bus.

The embedded reconfiguration streamer has the highest priority, followed by the reconfiguration interface, followed by the NPDME. When two feature blocks are trying to access the same transceiver channel on the same clock cycle, the feature block with the highest priority is given access. The only exception is when a lower priority feature block is in the middle of a read/write operation and a higher priority feature block tries to access the same channel. In this case, the higher-priority feature block must wait until the lower-priority feature block finishes the read/write operation.

When you enable NPDME in your design, you must either:
  • Connect an Avalon® memory-mapped interface master to the reconfiguration interface.
  • Connect the reconfig_clock and reconfig_reset ports, and ground the reconfig_write, reconfig_read, reconfig_address, and reconfig_writedata ports of the reconfiguration interface. If you do not connect the reconfiguration interface signals appropriately, the NPDME does not function properly.