E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

6.9.2. HDL Ports/Interfaces

Table 67.  HDL Ports/Interfaces when the Reset Controller is in Automatic Mode
Port Name Direction Clock Domain Width Description
reset Input Asynchronous Number of channels Resets TX and RX when asserted. Visible when Enable individual TX and RX resets is disabled. When the Native PHY is configured in PAM4 high data rate mode, the bus width equals the number of data channels parameter in the GUI divided by two.
tx_reset Input Asynchronous Number of channels Resets TX when asserted. Visible when Enable individual TX and RX resets is enabled. When the Native PHY is configured in PAM4 high data rate mode, the bus width equals the number of data channels parameter in the GUI divided by two.
rx_reset Input Asynchronous Number of channels Resets RX when asserted. Visible when Enable individual TX and RX resets is enabled. When the Native PHY is configured in PAM4 high data rate mode, the bus width equals the number of data channels parameter in the GUI divided by two.
tx_ready Output Asynchronous Number of channels

Status signal to indicate when TX resets sequencing is complete.

Deasserts during TX reset assertion.

Asserts a few clock cycles after deassertion of TX resets.

rx_ready Output Asynchronous Number of channels

Status signal to indicate when RX resets sequencing is complete.

Deasserts during RX reset assertion.

Asserts a few clock cycles after deassertion of RX resets.

tx_pma_ready Output Asynchronous Number of channels One per channel. Indicates transceiver channel Transmit calibration completed.
rx_pma_ready Output Asynchronous Number of channels One per channel. Indicates transceiver channel CDR calibration completed.

Did you find the information on this page useful?

Characters remaining:

Feedback Message