E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

7.7. Multiple Reconfiguration Profiles

You should enable multiple configurations or profiles in the same Native PHY IP for performing dynamic reconfiguration. This allows the IP Parameter Editor to create, store, and analyze the parameter settings for multiple configurations or profiles. The Native PHY can generate configuration files for all profiles in the SystemVerilog, MIF, or C header file formats. The files are located in the <IP instance name>/altera_xcvr_native_s10_etile_181/synth/reconfig subfolder of the IP instance with the configuration profile index added to the filename. For example, the configuration file for Profile 0 is stored as <filename_CFG0.sv>. The Intel® Quartus® Prime Timing Analyzer includes the necessary timing paths for all configurations based on initial and target profiles. You can also generate full reconfiguration files or reduced configuration files that contain only the attributes that differ between the multiple configured profiles. You can create up to eight reconfiguration profiles (Profile 0 to Profile 7) at a time for each Native PHY instance.

The configuration files generated by Native PHY IP also include PMA analog attributes.

You can use the multiple reconfiguration profiles feature without using the embedded reconfiguration streamer feature. When using the multiple reconfiguration profiles feature by itself, you must write the logic to reconfigure all entries that are different between the profiles while moving from one profile to another.

Note: You must ensure that none of the profiles in the Native PHY IP gives error messages, else the IP generation fails. The Native PHY IP core only validates the current active profile dynamically. For example, if you store a profile with error messages in the Native PHY IP and load another profile without any error messages, the error messages disappear in the IP. You are allowed to generate the IP, but the generation fails.

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