E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.3. rsfec_top_rx_cfg

Description Address Addressing Mode
RS-FEC RX configuration register 0x14 32-bits
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
31:28 loopback_tx2rx

FEC RX Bypass

Setting this bit enable loopback from TX RS-FEC to RX RS-FEC instead of getting from PMA interface. This is one bit per lane [bit0=lane0]

RW

RO

-

0x0
13:12 core_rx_out_sel3

RS-FEC RX Output Select For Lane 3

Indicates which data to select for rsfec core TX input. All lanes should have same selection for EHIP and RS-FEC_DIRECT_100G modes. Does not work for TX Select of Elane and Loopback

2'b00 : Bypass RS-FEC RX paths - data from PMA interface fec / pcs path (normal bypass)

2'b01 : Select output of RS-FEC RX.

2'b10 : Bypass RS-FEC RX paths - data from PMA interface fec path for both ehip and elane

2'b11 : Debug Mode - Select Loopback from EHIP TX Data.

RW

RO

-

0x0
9:8 core_rx_out_sel2

RS-FEC RX Output Select For Lane 2

Indicates which data to select for rsfec core TX input. All lanes should have same selection for EHIP and RS-FEC_DIRECT_100G modes. Does not work for TX Select of Elane and Loopback

2'b00 : Bypass RS-FEC RX paths - data from PMA interface fec / pcs path (normal bypass)

2'b01 : Select output of RS-FEC RX.

2'b10 : Bypass RS-FEC RX paths - data from PMA interface fec path for both ehip and elane

2'b11 : Debug Mode - Select Loopback from EHIP TX Data.

RW

RO

-

0x0
5:4 core_rx_out_sel1

RS-FEC RX Output Select For Lane 1

Indicates which data to select for rsfec core TX input. All lanes should have same selection for EHIP and RS-FEC_DIRECT_100G modes. Does not work for TX Select of Elane and Loopback

2'b00 : Bypass RS-FEC RX paths - data from PMA interface fec / pcs path (normal bypass)

2'b01 : Select output of RS-FEC RX.

2'b10 : Bypass RS-FEC RX paths - data from PMA interface fec path for both ehip and elane

2'b11 : Debug Mode - Select Loopback from EHIP TX Data.

RW

RO

-

0x0
1:0 core_rx_out_sel0

RS-FEC RX Output Select For Lane 0

Indicates which data to select for rsfec core TX input. All lanes should have same selection for EHIP and RS-FEC_DIRECT_100G modes. Does not work for TX Select of Elane and Loopback

2'b00 : Bypass RS-FEC RX paths - data from PMA interface fec / pcs path (normal bypass)

2'b01 : Select output of RS-FEC RX.

2'b10 : Bypass RS-FEC RX paths - data from PMA interface fec path for both ehip and elane

2'b11 : Debug Mode - Select Loopback from EHIP TX Data.

RW

RO

-

0x0

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