E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

10.3.1. Debug Parameters for the E-Tile Transceiver IP in the Parameter Editor

You must enable the following parameters in the E-Tile Transceiver PHY Intel FPGA IP.
Table 85.  Parameters to Enable Debugging in the E-Tile Transceiver PHY IP
Parameter Description
Enable Dynamic Reconfiguration Allows you to change the behavior of the transceiver channels and PLLs without powering down the device.
Enable Native PHY Debug Master Endpoint(NPDME) Allows you to access the transceiver and PLL registers through System Console. When you recompile your design, Intel® Quartus® Prime software inserts the debug fabric and embedded logic.
Enable control and status registers Enables soft registers to read status signals and write control signals on the PHY interface through the embedded debug.
Enable PRBS Soft Accumulators Enables soft logic for performing PRBS bit and error accumulation when you use the hard PRBS generator and checker.

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