E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

F. Hold Timing Violation

When using more than one instance of the E-tile Native PHY IP, you may see unexpected hold time violations. The violations are caused by EMIB registers clocked with two different clocks coming from the PMA channels of different Native PHY IP instances causing the IP to have false paths between channels of the implemented Native PHY IP instance.

You must implement cross-IP Synopsys design constraints (.sdc) to cut the false paths between channels from different Native PHY IP instances.

Note: This requirement is for Intel® Stratix® 10 devices only, not Intel® Agilex™ devices.

The following figure illustrates a Native PHY IP instance with four channels instantiated.

  • Timing paths between the same channel are valid paths and should be kept for clock skew control.
  • Timing paths across adjacent channels are invalid paths and must be cut by setting a false path between the two nodes in an .sdc file.
  • The Native PHY IP implements set_false_path between all adjacent channels within the Native PHY IP.
  • Timing paths across channels from different Native PHY IP instances are also invalid and must be cut by setting a false path between the two nodes in an .sdc file.
Figure 155. Native PHY IP Instance with Four Channels Instantiated

Example 1: Correct Timing Paths Between the Same Channel

From node:

xcvr_native_s10_etile_0|g_xcvr_native_insts[0].ct3_xcvr_native_inst|inst_ct3_xcvr_channel|inst_ct1_hssi_pldadapt_tx~aib_tx_internal_div.reg

To node:

xcvr_native_s10_etile_0|g_xcvr_native_insts[0].ct3_xcvr_native_inst|inst_ct3_xcvr_channel|inst_ct1_hssi_pldadapt_tx~s2_6_0__aibadpt__aib_fabric_tx_transfer_clk.reg

Example 2: Incorrect Timing Paths Across Adjacent Channels

From node:

xcvr_native_s10_etile_0|g_xcvr_native_insts[0].ct3_xcvr_native_inst|inst_ct3_xcvr_channel|inst_ct1_hssi_pldadapt_tx~aib_tx_internal_div.reg

To node:

xcvr_native_s10_etile_0|g_xcvr_native_insts[2].ct3_xcvr_native_inst|inst_ct3_xcvr_channel|inst_ct1_hssi_pldadapt_tx~s2_6_0__aibadpt__aib_fabric_tx_transfer_clk.reg

Example 3: Incorrect Timing Paths Across Channels from Different Native PHY IP Instances

The following figure shows a design with more than one IP instance each with a Native PHY IP instantiated.

Figure 156. Two Native PHY IP Instances, Each with Four Channels Instantiated

From node:

CLIENT_BK[4]|xcvr_native_s10_etile_0|g_xcvr_native_insts[0].ct3_xcvr_native_inst|inst_ct3_xcvr_channel|inst_ct1_hssi_pldadapt_tx~aib_tx_internal_div.reg

To node:

CLIENT_BK[5]|xcvr_native_s10_etile_0|g_xcvr_native_insts[0].ct3_xcvr_native_inst|inst_ct3_xcvr_channel|inst_ct1_hssi_pldadapt_tx~s2_6_0__aibadpt__aib_fabric_tx_transfer_clk.reg

Even though both nodes are from channel 0, they are from two different instances of Native PHY IP. In this case, it is not possible to set a false path at the Native PHY IP instance level, so you must set a false path through a high-level .sdc file in the project.

The previous figure shows this additional integrator .sdc file outside the Native PHY IP, where the appropriate timing paths need to be cut. Intel recommends that you:

  1. Locate the specific timing paths that are invalid in your design (paths across different channels that are not already cut by Native PHY IP instances).
  2. Then target those paths in your high-level .sdc file.

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