E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

7.15. Timing Closure Recommendations

Intel recommends that you enable the multiple reconfiguration profiles feature in the E-tile Native PHY IP core if any of the modified or target configurations involve changes to RS-FEC settings. Using multiple reconfiguration profiles is optional if the reconfiguration involves changes to only PMA settings such as TX Attenuation Value (VOD) swing or refclk switching. When performing a dynamic reconfiguration, you must:

  • Include constraints to create the extra clocks for all modified or target configurations at the RS-FEC -FPGA fabric interface. Clocks for the base configuration are created by the Intel® Quartus® Prime software. These clocks enable the Intel® Quartus® Prime Pro Edition to perform static timing analysis for all the transceiver configurations and their corresponding FPGA fabric core logic blocks.
  • Include the necessary false paths between the RS-FEC – FPGA fabric interface and the core logic.

For example, you can perform dynamic reconfiguration to switch the datapath from PMA direct to RS-FEC using the multiple reconfiguration profiles feature.

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