E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

7.13. Ports and Parameters

The reconfiguration interface is integrated in the Native PHY instance. Instantiate the Native PHY IP cores in the IP Parameter Editor by clicking Tools > IP Catalog. You can define parameters for IP cores by using the IP-core-specific Parameter Editor. To expose the reconfiguration interface ports, select the Enable dynamic reconfiguration option when parameterizing the IP core. You can share the reconfiguration interface among all the channels by turning on Share reconfiguration interface when parameterizing the IP core. When this option is enabled, the IP core presents a single reconfiguration interface for the dynamic reconfiguration of all channels. Address bits [18:0] provide the register address in the reconfiguration space of the selected channel. The remaining address bits of the reconfiguration address specify the selected logical channel. For example, if there are four channels in the Native PHY IP instance, reconfig_address[18:0] specifies the address and reconfig_address[20:19] are binary encoded to specify the four channels. For example, 2'b01 in reconfig_address[20:19] specifies logical channel 1.

The following figure shows the signals available when the Native PHY IP core is configured for four channels and the Share reconfiguration interface option is enabled.

Figure 108. Reconfiguration Interface Ports with Shared Native PHY Reconfiguration Interface
Table 70.  Reconfiguration Interface Ports with Shared Native PHY Reconfiguration InterfaceThe reconfiguration interface ports when Share reconfiguration interface is enabled. <N> represents the number of channels.

Port Name

Direction

Clock Domain

Description

reconfig_clk

Input

N/A

The clock frequency is 100 to 162 MHz.

reconfig_reset

Input

reconfig_clk

Resets the Avalon® memory-mapped interface. Asynchronous assertion and synchronous deassertion.

reconfig_write

Input

reconfig_clk

Write enable signal. Signal is active high.

reconfig_read

Input

reconfig_clk

Read enable signal. Signal is active high.

reconfig_address[log2<N>+18:0]

Input

reconfig_clk

Address bus. The lower 19 bits specify address, and the upper bits specify the channel.

reconfig_writedata[7:0]

Input

reconfig_clk

An 8-bit data write bus. Data to be written into the address indicated by reconfig_address.

reconfig_readdata[7:0]

Output

reconfig_clk

An 8-bit data read bus. Valid data is placed on this bus after a read operation. Signal is valid after reconfig_waitrequest goes high and then low.

reconfig_waitrequest

Output

reconfig_clk

A one-bit signal that indicates that the Avalon® memory-mapped interface is busy. Keep the Avalon® memory-mapped interface command asserted until the interface is ready to proceed with the read/write transfer.

When Share reconfiguration interface is disabled and Provide separate interface for each channel is enabled, the Native PHY IP core provides an independent reconfiguration interface for each channel. For example, when a reconfiguration interface is not shared for a four-channel Native PHY IP instance, reconfig_address_ch0[18:0] corresponds to the reconfiguration address bus of logical channel 0, reconfig_address_ch1[18:0] correspond to the reconfiguration address bus of logical channel 1, reconfig_address_ch2[18:0] corresponds to the reconfiguration address bus of logical channel 2, and reconfig_address_ch3[18:0] correspond to the reconfiguration address bus of logical channel 3.

The following figure shows the signals available when the Native PHY is configured for four channels and the Share reconfiguration interface option is not enabled and Provide separate interface for each channel is enabled.

Figure 109. Signals Available with Independent Native PHY Reconfiguration Interfaces
Note: The RS-FEC reconfiguration interface is not separated for each channel.
Table 71.  Reconfiguration Interface Ports with Independent Native PHY Reconfiguration InterfaceThe reconfiguration interface ports when Share reconfiguration interface is disabled. <N> represents the number of channels.

Port Name

Direction

Clock Domain

Description

reconfig_clk_ch<N-1>, ...,reconfig_clk_ch0

Input

N/A

The clock frequency is 100-162 MHz.

reconfig_reset_ch<N-1>, ...,reconfig_reset_ch0

Input

reconfig_clk_ch#

Resets the Avalon® memory-mapped interface. Asynchronous assertion and synchronous deassertion.

reconfig_write_ch<N-1>, ...,reconfig_write_ch0

Input

reconfig_clk_ch#

Write enable signal. Signal is active high.

reconfig_read_ch<N-1>, ...,reconfig_read_ch0

Input

reconfig_clk_ch#

Read enable signal. Signal is active high.

reconfig_address_ch<N-1>[18:0], ...,reconfig_address_ch0[18:0]

Input

reconfig_clk_ch#

A 19-bit address bus for each channel.

reconfig_writedata_ch<N-1>[7:0], ...,reconfig_writedata_ch0[7:0]

Input

reconfig_clk_ch#

An 8-bit data write bus for each channel. Data to be written into the address indicated by reconfig_address.

reconfig_readdata_ch<N-1>[7:0], ...,reconfig_readdata_ch0[7:0]

Output

reconfig_clk_ch#

An 8-bit data read bus for each channel. Valid data is placed on this bus after a read operation. Signal is valid after reconfig_waitrequest goes high and then low.

reconfig_waitrequest_ch<N-1>, ...,reconfig_waitrequest_ch0

Output

reconfig_clk_ch#

A one-bit signal for each channel that indicates that the Avalon® memory-mapped interface interface is busy. Keep the Avalon® memory-mapped interface command asserted until the interface is ready to proceed with the read/write transfer.

Table 72.   Avalon® Memory-Mapped Interface ParametersThe following parameters are available in the Dynamic Reconfiguration tab of the Transceiver Native PHY parameter editors.

Parameter

Value

Description

Share reconfiguration interface

On/Off

Enables you to use a single reconfiguration interface to control all channels. Off by default. If enabled, the uppermost bits of reconfig_address identifies the active channel. The lower 20 bits specify the reconfiguration address. Binary encoding is used to identify the active channel (available only for Transceiver Native PHY). Enable this option, if desired, when the Native PHY is configured with more than one channel.

Enable dynamic reconfiguration

On/Off

Enables the reconfiguration interface. Off by default. The reconfiguration interface is exposed when this option is enabled.

Enable Native PHY Debug Master Endpoint

On/Off

When enabled, the Native PHY Debug Master Endpoint (NPDME) is instantiated and has access to the Avalon® memory-mapped interface of the Native PHY. You can access certain test and debug functions using System Console with the NPDME. Refer to the "Embedded Debug Features" section for more details about NPDME.

Enable capability registers

On/Off

Enables capability registers. These registers provide high-level information about the transceiver channel's configuration.

Set user-defined IP identifier

User-defined

Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled.

Enable control and status registers

On/Off

Enables soft registers for reading status signals and writing control signals on the PHY interface through the NPDME or reconfiguration interface.

Configuration file prefix

User-defined

Specifies the file prefix used for generating configuration files. Use a unique prefix for configuration files for each variant of the Native PHY.

Generate SystemVerilog package File

On/Off

Creates a SystemVerilog package file that contains the current configuration data values for all reconfiguration addresses. Disabled by default.

Generate C header file

On/Off

Creates a C header file that contains the current configuration data values for all reconfiguration addresses. Disabled by default.

Generate MIF (Memory Initialize File)

On/Off

Creates a MIF file that contains the current configuration data values for all reconfiguration addresses. Disabled by default.

Enable multiple reconfiguration profiles

On/Off

Use the Parameter Editor to store multiple configurations. The parameter settings for each profile are tabulated in the Parameter Editor.

Enable embedded reconfiguration streamer

On/Off

Embeds the reconfiguration streamer into the Native PHY IP core, and automates the dynamic reconfiguration process between multiple predefined configuration profiles.

Generate reduced reconfiguration files

On/Off

Enables the Native PHY IP core to generate reconfiguration files that contain only the attributes that differ between multiple profiles.

Number of reconfiguration profiles

1 to 8

Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled.

Store current configuration to profile

0 to 7

Selects which reconfiguration profile to store.

Store configuration to selected profile

N/A

Stores the current Native PHY parameter settings to the profile specified by Store current configuration to profile specified.

Load configuration from selected profile

N/A

Loads the current Native PHY parameter settings to the profile specified by Store current configuration to profile specified.

Clear selected profile

N/A

Clears the stored Native PHY parameter settings for the profile specified by the Store current reconfiguration to profile parameter. An empty profile defaults to the current parameter settings of the Native PHY. In other words, an empty profile reflects the Native PHY current parameter settings.

Clear all profiles

N/A

Clears the Native PHY IP parameter settings for all profiles.

Refresh selected profile

N/A

Equivalent to clicking the Load configuration from selected profile and Store configuration to selected profile buttons in sequence. This operation loads the parameter settings from stored profile specified by the Store current configuration to profile parameter and then stores the parameters back to the profile.

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