E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

3.1.9.2. Dedicated Balanced PLL Reference Clock Tree

Once bonding is enabled, use refclk0 on the hardware. This clock is connected to the transceiver through a dedicated balanced clock tree. You do not need to do anything on Native PHY side. You can select any reference clock; however, the fitter checks that your selection on the reference clock number in the Native PHY is assigned to refclk0 in the Intel® Quartus® Prime settings file (.qsf) assignments.

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