6.5.3. Reset Controller Bypass
The TRS block in the reset controller, which prevents multiple transceivers from being in reset at the same time is not implemented.
If you have multiple E-tile Native PHY IP core instances on a single E-tile, make sure that you assert/deassert reset to a single transceiver channel in an E-tile at a time. For example, if you instantiate three E-tile Native PHY IP cores with the following configurations:
- Instance A with one transceiver channel with RS-FEC disabled and the reset controller in automatic mode
- Instance B with four transceiver channels with RS-FEC enabled in aggregate mode and the reset controller in manual mode
- Instance C with two transceiver channels with RS-FEC enabled in fractured mode and the reset controller bypassed
If you want to reset instances A or B, you cannot assert/deassert reset signals on instance C at the same time.
If you want to reset any channel in instance C, you cannot reset instance A or B. You can only reset a single channel inside instance C at a time. If you previously asserted reset on instance A, ensure that tx_ready and rx_ready are deasserted on instance A. If you previously deasserted reset on instance A, ensure that tx_ready and rx_ready are asserted on instance A. Do not assert the tx_reset_req or rx_reset_req on instance B.
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