E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

4.2.6. PMA Direct 100GE Gbps (25 Gbps x 4) (FEC On)

This use case is implemented in the case of multi-lane protocols like 100GbE, for example. This uses four transceiver lanes of 25 Gbps each, where all four lanes must use the same FEC block. FEC is clocked by one of the four channels and you can configure this in the Native PHY IP core Parameter Editor. There is an inherent dependency between channels in this configuration. However, for applications like 100 GbE, dependency is acceptable and sometimes required. For each of the four channels with Core Interface FIFOs in Phase Compensation mode, connect tx_clkout (402.832031 MHz) to tx_coreclkin and rx_coreclkin. If you use any other source for tx_coreclkin or rx_coreclkin, make sure tx_coreclkin and rx_coreclkin have 0 PPM difference with the tx_clkout. The figure below assumes that all four channels have a common reference clock source (0 PPM between all four channels). You can also connect tx_clkout from any of the four channels to the tx_coreclkin and rx_coreclkin of all four channels. This helps keep the four-lane data synced on a single clock domain.

Figure 72. PMA Direct 100GE Gbps (25 Gbps x 4 per lane) (FEC On)RS-FEC is also clocked by the TX PMA generated clock.

For clocking within the EHIP, see the E-tile Hard IP for Ethernet Intel® FPGA IP User Guide.

Did you find the information on this page useful?

Characters remaining:

Feedback Message