E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

3.1. Physical Medium Attachment (PMA) Architecture

The PMA acts as the analog front end for the E-tile transceivers.

The PMA transmits and receives high-speed serial data depending on the transceiver channel configuration. The PMA transmitter serializes parallel data, and the PMA receiver deserializes serial data.

The E-tile PMA GXE channels support both NRZ and PAM4 data formats. A single bit of data is transmitted/received in one UI in NRZ mode, while two bits of data are transmitted/received in one UI in PAM4 mode. The transceiver can operate up to 28.9 Gbps in NRZ mode and 57.8 Gbps in PAM4 mode.

The PMA supports the following parallel data widths:

  • 16 bits (NRZ mode only)
  • 20 bits (NRZ mode only)
  • 32 bits (NRZ, PAM4)
  • 40 bits (NRZ, PAM4)
  • 64 bits (PAM4 high data rate mode only)

Supported protocols include, but are not limited to:

  • IEEE 802.3ap (10GBASE-KR)
  • IEEE 802.3bj (100G-KR4, 100G-CR4)
  • IEEE 802.3bm (CAUI4)
  • IEEE 802.3bs (400G Ethernet)
  • IEEE 802.3cd (50GBASE-CR, 50GBASE-KR)
  • IEEE 802.3by (25GBASE-CR, 25GBASE-KR)
  • CEI-25G-LR
  • CEI-28G-VSR/SR/MR
  • CEI-56G-VSR/MR/LR
  • 32GFC
Figure 47. PMA Architecture Block Diagram

A given E-tile has nine reference clock pins linked to a reference clock network, which is shared across all of the 24 PMA channels within a tile. refclk_0 routing is skew-balanced across all the channels and is used for TX PMA bonding. Additionally, each channel has two clock input ports (refclk_in_A and refclk_in_B) which drive dedicated clocking resources. Muxing options allow you to select the desired external reference clock pin to drive the individual clock input ports for each PMA channel. The block diagram below demonstrates the muxing capability.

Figure 48. Dynamically Selected Reference Clocks

For more details, refer to Clock Network.

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