E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

1.2.3. Intel® Stratix® 10 DX P-Tile and E-Tile Configurations

Intel® Stratix® 10 DX devices combine P-tiles for processor connectivity along with E-tiles for Ethernet support.
Table 3.  Available E-Tile Transceiver Channels in Intel® Stratix® 10 DX FPGA Devices
Intel® Stratix® 10 DX Device Name Number of E-Tile Transceiver Channels Available E-Tile Transceiver Channel Locations
DX 1100 16 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15, 20, 21, 22, 23
DX 2100 24 0 through 23
DX 2800 8 0, 1, 2, 3, 12, 13, 14, 15

Refer to the respective Pin-Out Files for Intel® FPGA Devices to find the actual number of reference clocks available in each device.

Figure 7.  Intel® Stratix® 10 DX Device with 1 P-Tile and 1 E-Tile (32 Transceiver Channels)
Figure 8.  Intel® Stratix® 10 DX Device with 3 P-Tiles and 1 E-Tile (84 Transceiver Channels)
Figure 9.  Intel® Stratix® 10 DX Device with 4 P-Tiles and 1 E-Tile (84 Transceiver Channels)

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