7.14.1. Native PHY Debug Master Endpoint (NPDME)
The NPDME is a JTAG-based Avalon® memory-mapped interface master that provides access to the transceiver registers through the system console. You can enable NPDME using the Enable Native PHY Debug Master Endpoint option available under the Dynamic Reconfiguration tab in the Native PHY IP cores. When using NPDME, the Intel® Quartus® Prime software inserts the debug interconnect fabric to connect with USB, JTAG, or other net hosts. Select the Share Reconfiguration Interface parameter when the Native PHY IP instance has more than one channel. The Transceiver Toolkit, a useful tool in debugging transceiver links, requires NPDME.
When you enable NPDME in your design, you must do one of the following:
- Connect an Avalon® memory-mapped interface master to the reconfiguration interface.
- Connect the reconfig_clk, reconfig_reset signals and ground the reconfig_write, reconfig_read, reconfig_address, and reconfig_write data signals of the reconfiguration interface if not being driven by other core logic. If you do not connect the reconfiguration interface signals appropriately, the NPDME has no clock or reset and functions unexpectedly. Refer to the example connection below (this is an example of a single channel with no internal logic driving the reconfig interface):
.reconfig_clk (mgmt_clk), .reconfig_reset (mgmt_reset), .reconfig_write (1'b0), .reconfig_address (19'b0), .reconfig_read (1'b0), .reconfig_writedata (8'b0),
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