E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

2.2.8. Reset Parameters

The Native PHY IP Core reset parameters provide reset control for the PMA interface and adapter.
Figure 35. Reset Options
Table 29.  Reset Parameters
Parameter Value Description
Enable manual reset On/Off When enabled, sets manual reset mode. You must control all reset signals for the device.
Enable fast simulation for controller On/Off When enabled, the IP uses reduced reset time for reset controller in simulation.
Enable fast simulation for sequencer On/Off When enabled, the IP disables reset staggering in simulation. The reset behavior in simulation is different from the reset behavior in hardware.
Enable individual TX and RX reset On/Off When enabled, the IP uses tx_reset and rx_reset input ports to control TX and RX individually, otherwise uses reset input ports to control both TX and RX.
Enable individual channel reset On/Off When enabled, you can control the channels individually.
Enable TX/RX reset sequencing On/Off When enabled, the IP staggers the deassertion of the TX reset before the RX reset. That is, tx_reset deassertion gates rx_reset deassertion.

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