E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

6.2.2. Selecting the Reset Controller's Clock Source

When you instantiate a Native PHY IP, the software automatically instantiates Master Transceiver Reset Sequencer (TRS) and Local TRS (LTRS) blocks. Use the Intel® Quartus® Prime Pro Edition assignment settings editor to provide a 25, 100, or 125 MHz free-running and stable clock to OSC_CLK_1 for the proper functionality of the two blocks. To set the OSC_CLK_1 frequency in Intel® Quartus® Prime, follow these steps:
  1. Select Assignment > Settings.
  2. Click Device/Board in the top right corner.
  3. Select Device and Pin Options.
  4. Select 25 MHz OSC_CLK_1 pin, 100 MHz OSC_CLK_1 pin, or 125 MHz OSC_CLK_1 pin as the Configuration clock source.
Figure 76. Device and Pin Options

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