E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5. RS-FEC Registers

The delay between RS-FEC register reads should be at least 10 μs. There is no such requirement for register writes. As a result, RS-FEC register back-to-back writes are allowed.

In order to get reliable readouts of the registers with addresses greater than 0x100, ensure RS-FEC has a valid clock.

Reconfiguration and status monitoring of the RS-FEC block in the E-tile Native PHY IP core is provided through a dedicated Avalon® memory-mapped interface. This interface specifically reads and writes the control and status registers associated with the RS-FEC block. A separate Avalon® memory-mapped interface, called the channel Avalon® memory-mapped interface, reads and writes the control and status registers associated with the other blocks in the E-tile Native PHY IP core.

The Avalon® memory-mapped interface for the RS-FEC consists of eight interface ports exposed at the top level of the Native PHY IP core.

Table 83.  RS-FEC Avalon® Memory-Mapped Interface Ports
Port Name Direction   Clock Domain Width
reconfig_rsfec_clk Input wire N/A  
reconfig_rsfec_reset Input wire reconfig_rsfec_clk  
reconfig_rsfec_write Input wire reconfig_rsfec_clk  
reconfig_rsfec_read Input wire reconfig_rsfec_clk  
reconfig_rsfec_address Input wire reconfig_rsfec_clk [10:0]
reconfig_rsfec_writedata Input wire reconfig_rsfec_clk [7:0]
reconfig_rsfec_readdata Output wire reconfig_rsfec_clk [7:0]
reconfig_rsfec_waitrequest Output wire reconfig_rsfec_clk  

The reconfig_rsfec_clk input must be driven by a 100-125 MHz clock. The same clock can be used for this input as for the channel Avalon® memory-mapped interface.

The reconfig_rsfec_reset input must be asserted for at least one clock cycle of the reconfiguration clock after the device has entered user mode. The Reset IP can be used to provide this reset signal.

The reconfig_rsfec_write and reconfig_rsfec_read inputs are used to indicate to the Avalon® memory-mapped interface whether a read or write operation is desired. The reconfig_rsfec_address input is used for both read and write operations and indicates which register address is targeted during the current Avalon® Memory-Mapped Interface access operation.

The reconfig_rsfec_writedata and reconfig_rsfec_readdata contain the data to be written to or the data read from the register address set by the 11 bit reconfig_rsfec_address input.

The reconfig_rsfec_writedata and reconfig_rsfec_readdata ports are 8 bits wide. The RS-FEC registers, in the hardware, are 32 bits wide, but they use 4 byte increment addressing, so the 32 bit register can be addressed as four 8 bit registers with contiguous byte addresses.

For example, the least-significant byte (lowest order byte) of register 0x04 (where register address 0x04 is considered as a 32 bit register address) is accessed by reading 8 bits from or writing 8 bits to address 0x04. To get the next most significant byte of the same 32 bit register, read 8 bits from or write 8 bits to address 0x05. To get the rest of the register, use addresses 0x06 and 0x07. The next 32 bit register has an address of 0x08. In other words, the 32 bit register addresses increment by 4 bytes for each register.

Effectively, the registers are addressed, read, and written one byte at a time. This matches the hardware implementation of the Avalon® memory-mapped interface.

The reconfig_rsfec_waitrequest output asserts when the Avalon® memory-mapped interface is busy servicing an Avalon® Memory-Mapped Interface operation and deasserts when the Avalon® Memory-Mapped Interface is available for the next operation.

Table 84.  RS-FEC Registers
Address Name Description Reset
0x04 rsfec_top_clk_cfg RS-FEC Clock configuration register 0x0000 0F00
0x10 rsfec_top_tx_cfg RS-FEC TX configuration register 0x0000 0000
0x14 rsfec_top_rx_cfg RS-FEC RX configuration register 0x0000 0000
0x20 tx_aib_dsk_conf Defines the configuration fields for TX Deskew 0x0000 0000
0x30 rsfec_core_cfg RS-FEC core configuration 0x0000 0000
0x40 rsfec_lane_cfg_0 RS-FEC per lane configuration 0x0000 0000
0x44 rsfec_lane_cfg_1
0x48 rsfec_lane_cfg_2
0x4C rsfec_lane_cfg_3
0x104 tx_aib_dsk_status Status fields for TX Deskew 0x0000 0000
0x108 rsfec_debug_cfg Extra config/debug on fec_clock 0x0000 0000
0x120 rsfec_lane_tx_stat_0 RS-FEC per lane TX status 0x0000 0000
0x124 rsfec_lane_tx_stat_1
0x128 rsfec_lane_tx_stat_2
0x12C rsfec_lane_tx_stat_3
0x130 rsfec_lane_tx_hold_0 RS-FEC per lane TX status hold 0x0000 0000
0x134 rsfec_lane_tx_hold_1
0x138 rsfec_lane_tx_hold_2
0x13C rsfec_lane_tx_hold_3
0x140 rsfec_lane_tx_inten_0 RS-FEC per lane TX status hold interrupt - set to 1 to enable rsfec_lane_tx lane interrupt 0x0000 0000
0x144 rsfec_lane_tx_inten_1
0x148 rsfec_lane_tx_inten_2
0x14C rsfec_lane_tx_inten_3
0x150 rsfec_lane_rx_stat_0 RS-FEC per lane RX status 0x0000 0000
0x154 rsfec_lane_rx_stat_1
0x158 rsfec_lane_rx_stat_2
0x15C rsfec_lane_rx_stat_3
0x160 rsfec_lane_rx_hold_0 RS-FEC per lane RX status hold 0x0000 0000
0x164 rsfec_lane_rx_hold_1
0x168 rsfec_lane_rx_hold_2
0x16C rsfec_lane_rx_hold_3
0x170 rsfec_lane_rx_inten_0 RS-FEC per lane RX status hold interrupt - set to 1 to enable rsfec_lane_rx lane interrupt 0x0000 0000
0x174 rsfec_lane_rx_inten_1
0x178 rsfec_lane_rx_inten_2
0x17C rsfec_lane_rx_inten_3
0x180 rsfec_lanes_rx_stat RS-FEC combined lanes RX status 0x0000 0000
0x188 rsfec_lanes_rx_hold RS-FEC combined lanes RX hold status 0x0000 0000
0x18C rsfec_lanes_rx_inten RS-FEC combined lanes RX interrupt enable - set to 1 to enable rsfec_lanes RX lane interrupt 0x0000 0000
0x1A0 rsfec_ln_mapping_rx_0 RS-FEC FEC lane mapping 0x0000 0000
0x1A4 rsfec_ln_mapping_rx_1
0x1A8 rsfec_ln_mapping_rx_2
0x1AC rsfec_ln_mapping_rx_3
0x1B0 rsfec_ln_skew_rx_0 RS-FEC lane skew 0x0000 0000
0x1B4 rsfec_ln_skew_rx_1
0x1B8 rsfec_ln_skew_rx_2
0x1BC rsfec_ln_skew_rx_3
0x1C0 rsfec_cw_pos_rx_0 RS-FEC codeword bit position on RX 0x0000 0000
0x1C4 rsfec_cw_pos_rx_1
0x1C8 rsfec_cw_pos_rx_2
0x1CC rsfec_cw_pos_rx_3
0x1D0 rsfec_core_ecc_hold RS-FEC SRAM ECC status hold 0x0000 0000
0x1E0 rsfec_err_inj_tx_0 RS-FEC error injection mode 0x0000 0000
0x1E4 rsfec_err_inj_tx_1
0x1E8 rsfec_err_inj_tx_2
0x1EC rsfec_err_inj_tx_3
0x1F0 rsfec_err_val_tx_0 RS-FEC per lane error injection status 0x0000 0000
0x1F4 rsfec_err_val_tx_1
0x1F8 rsfec_err_val_tx_2
0x1FC rsfec_err_val_tx_3
0x200 rsfec_corr_cw_cnt_0_lo RS-FEC number of FEC codewords with errors that were corrected (low word: bits 31 to 0) 0x0000 0000
0x208 rsfec_corr_cw_cnt_1_lo
0x210 rsfec_corr_cw_cnt_2_lo
0x218 rsfec_corr_cw_cnt_3_lo
0x204 rsfec_corr_cw_cnt_0_hi RS-FEC number of FEC codewords with errors that were corrected (high word: bits 63 to 32) 0x0000 0000
0x20C rsfec_corr_cw_cnt_1_hi
0x214 rsfec_corr_cw_cnt_2_hi
0x21C rsfec_corr_cw_cnt_3_hi
0x220 rsfec_uncorr_cw_cnt_0_lo RS-FEC number of FEC codewords that could not be corrected due to too many errors (low word: bits 31 to 0) 0x0000 0000
0x228 rsfec_uncorr_cw_cnt_1_lo
0x230 rsfec_uncorr_cw_cnt_2_lo
0x238 rsfec_uncorr_cw_cnt_3_lo
0x224 rsfec_uncorr_cw_cnt_0_hi RS-FEC number of FEC codewords that could not be corrected due to too many errors (high word: bits 63 to 32) 0x0000 0000
0x22C rsfec_uncorr_cw_cnt_1_hi
0x234 rsfec_uncorr_cw_cnt_2_hi
0x23C rsfec_uncorr_cw_cnt_3_hi
0x240 rsfec_corr_syms_cnt_0_lo RS-FEC number of 10b symbols corrected for the lane (low word: bits 31 to 0) 0x0000 0000
0x248 rsfec_corr_syms_cnt_1_lo
0x250 rsfec_corr_syms_cnt_2_lo
0x258 rsfec_corr_syms_cnt_3_lo
0x244 rsfec_corr_syms_cnt_0_hi RS-FEC number of 10b symbols corrected for the lane (high word: bits 63 to 32) 0x0000 0000
0x24C rsfec_corr_syms_cnt_1_hi
0x254 rsfec_corr_syms_cnt_2_hi
0x25C rsfec_corr_syms_cnt_3_hi
0x260 rsfec_corr_0s_cnt_0_lo RS-FEC number of bits corrected 0->1 for the lane (low word: bits 31 to 0) 0x0000 0000
0x268 rsfec_corr_0s_cnt_1_lo
0x270 rsfec_corr_0s_cnt_2_lo
0x278 rsfec_corr_0s_cnt_3_lo
0x264 rsfec_corr_0s_cnt_0_hi RS-FEC number of bits corrected 0->1 for the lane (high word: bits 63 to 32) 0x0000 0000
0x26C rsfec_corr_0s_cnt_1_hi
0x274 rsfec_corr_0s_cnt_2_hi
0x27C rsfec_corr_0s_cnt_3_hi
0x280 rsfec_corr_1s_cnt_0_lo RS-FEC number of bits corrected 1->0 for the lane (low word: bits 31 to 0) 0x0000 0000
0x288 rsfec_corr_1s_cnt_1_lo
0x290 rsfec_corr_1s_cnt_2_lo
0x298 rsfec_corr_1s_cnt_3_lo
0x284 rsfec_corr_1s_cnt_0_hi RS-FEC number of bits corrected 1->0 for the lane (high word: bits 63 to 32) 0x0000 0000
0x28C rsfec_corr_1s_cnt_1_hi
0x294 rsfec_corr_1s_cnt_2_hi
0x29C rsfec_corr_1s_cnt_3_hi

All statistic registers are 64 bits, and you must do two 32-bit reads. Intel recommends that you enable the shadow_req[3:0] in offset address 0x108 explained in rsfec_debug_cfg before reading the statistics register and disable after reading it.

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