E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

3.3. Reed Solomon Forward Error Correction (RS-FEC) Architecture

The E-tile includes a Reed Solomon Forward Error Correction (RS-FEC) block.

For more basic RS-FEC information, refer to AN 846: Intel® Stratix® 10 Forward Error Correction.

The RS-FEC core supports the following standards:

  • 100GbE: IEEE 802.3 Clause 91
  • 100GbE with KP-FEC: IEEE 802.3 Clause 91
  • 128GFC: Fibre Channel Framing and Signaling - 4 (FC-FCS-4) Clause 5.6
  • 25GbE: IEEE 802.3 Clause 108
  • 32GFC: Fibre Channel Framing and Signaling - 4 (FC-FCS-4) Clause 5.4

100GbE with KP-FEC uses two physical PAM4 coded lanes, also called, 100 Gigabit Attachment Unit Interface (CAUI-2). It uses the RS(544,514) FEC. The two physical lanes are supported by bit-multiplexing the RS-FEC core’s four PMA lanes pairwise outside of the RS-FEC core. The remaining defined clients use the RS(528,514) FEC.

In the CPRI standard, the CPRI FEC refers to 32GFC. CPRI is like 32GFC except for the line rate, which is 24 Gbps.

Table 50.  Supported FEC Specifications in E-Tiles
Supported RS-FEC Type Compliance

RS-FEC (528, 514)

RS-FEC (544, 514)

IEEE 802.3 Clause 91
Table 51.  FEC Details in E-Tiles
Resource Description
Number of RS-FEC blocks per E-tile 6
Number of RS-FEC lanes per FEC block 4
RS-FEC block implementation Hard
RS-FEC block locations Between the transceiver interface and Ethernet Hard IP (EHIP_TOP)

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