AN 846: Intel® Stratix® 10 Forward Error Correction

ID 683805
Date 7/02/2018
Public
Document Table of Contents

1. Introduction

This application note explains forward error correction (FEC) theory and the Intel® Stratix® 10 device family's FEC capabilities.

Forward error correction is a powerful method of correcting errors that can occur on a serial link. Although very useful, it can be costly in both area and power when implemented in soft logic. For this reason, E-Tile and H-Tile devices provide hardened FEC blocks to address many important applications, such as:

  • 10 Gigabit Ethernet (GbE) (H-Tile)
  • 25GbE (E-Tile)
  • 100GbE (E-Tile)
  • 24.3 Gbps Common Public Radio Interface (CPRI) (E-Tile)
  • 128 gigabit fibre channel (GFC) (E-Tile)
Table 1.  FEC Type Comparison by Transceiver Tile
H-Tile E-Tile
Fire Code—NRZ Reed Solomon (RS) Code—NRZ Reed Solomon (RS) Code—PAM4
  • RS (2112, 2080) (in bits)
  • Binary code (operates on bits)
  • Lower gain (2-2.5 dB)
  • Moderate burst correction
  • Supports 802.3ap, 10GBASE-KR
  • RS-FEC: RS (528, 514, 7 ,10) (in symbols)
  • Non-binary code
  • Good gain (5-5.5 dB)
  • Corrects both random and burst errors
  • Supports 802.3bj, 100GBASE-KR4
  • KP-FEC: RS (544, 514, 15, 10) (in symbols)
  • Non-binary code
  • Very good gain (6-6.5 dB)
  • Corrects both random and burst errors
  • Supports 802.3bj, CEI 56G, 100GBASE-KP2

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