1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
5.5. Specifications
The IEEE802.3ap specification defines an insertion loss and return loss of 25 dB at 5.15625 GHz. The 1e-12 BER requirement is a system specification that is met with or without FEC.
The IEEE802.3bj specification specifies 100GBASE-KR4 for 100 Gbps operation using NRZ over four differential pairs where the insertion loss does not exceed 35 dB at 12.9 GHz. 100GBASE-KR4 uses:
- The PCS defined in Clause 82
- The RS-FEC defined in Clause 91
- The PMA defined in Clause 83
- The PMD defined in Clause 93
IEEE802.3bj also specifies 100GBASE-KP4 for 100 Gbps operation using PAM4 over two differential pairs where the insertion loss does not exceed 33 dB at 7 GHz. 100GBASE-KP4 uses:
- The PCS defined in Clause 82
- The RS-FEC defined in Clause 91
- The PMA and PMD defined in Clause 94
The CEI 56G long reach (LR) specification discusses multiple FECs, but the standard is KP4 FEC with PAM4. The 1e-15 BER requirement is a system specification met with FEC.