1. Introduction 2. Necessity of Error Correction 3. FEC Selection 4. FEC in Intel® Stratix® 10 H-Tile Devices 5. FEC in Intel® Stratix® 10 E-Tile Devices 6. FEC Implementation Using the E-Tile Channel Placement Tool 7. FEC in Practical Application 8. Hardware Results 9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
5.6.4. Alignment Marker Removal
After all PCS lanes are aligned and deskewed, the PCS lanes are multiplexed together in the proper order to reconstruct the original stream of blocks. At this point, the alignment markers are removed from the data stream.
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