AN 846: Intel® Stratix® 10 Forward Error Correction

ID 683805
Date 7/02/2018
Public
Document Table of Contents

4.1.4. L-Tile/H-Tile Implementation

Figure 6. Enhanced PCS Datapath Diagram

The KR FEC blocks in the Enhanced PCS are designed in accordance with the 10GBASE-KR FEC and 40GBASE-KR FEC specification of the IEEE 802.3 specification. The KR FEC implements the FEC as a sublayer between the PCS and PMA sublayers.

The FEC sublayer is optional and you can bypass it. When used, it provides additional margin to allow for variations in manufacturing and environmental conditions. FEC can achieve the following objectives:

  • Support a forward error correction mechanism for the 10GBASE-R/KR and 40GBASE-R/KR protocols
  • Support full duplex mode of the Ethernet MAC
  • Support the PCS, PMA, and Physical Medium Dependent (PMD) sublayers defined for the 10GBASE-R/KR and 40GBASE-R/KR protocols

KR FEC improves the BER performance of the system.

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