AN 846: Intel® Stratix® 10 Forward Error Correction

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ID 683805
Date 7/02/2018
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Necessity of Error Correction 3. FEC Selection 4. FEC in Intel® Stratix® 10 H-Tile Devices 5. FEC in Intel® Stratix® 10 E-Tile Devices 6. FEC Implementation Using the E-Tile Channel Placement Tool 7. FEC in Practical Application 8. Hardware Results 9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
2. Necessity of Error Correction x
2.1. Solutions to Transmission Errors 2.2. Error Correction Codes 2.3. What is FEC?
2.1. Solutions to Transmission Errors x
2.1.1. Parity and Cyclic Redundancy Check 2.1.2. Error Correction Code (ECC) Block Coding
2.3. What is FEC? x
2.3.1. FEC Definitions
3. FEC Selection x
3.1. Key Considerations when Choosing a FEC
4. FEC in Intel® Stratix® 10 H-Tile Devices x
4.1. Fire Code (802.3ap, 10GBASE-KR)
4.1. Fire Code (802.3ap, 10GBASE-KR) x
4.1.1. FEC Block Format 4.1.2. FEC Block Composition 4.1.3. FEC Sublayer for BASE-R PHYs 4.1.4. L-Tile/H-Tile Implementation
4.1.4. L-Tile/H-Tile Implementation x
4.1.4.1. Transcode Encoder 4.1.4.2. KR FEC Encoder 4.1.4.3. KR FEC Scrambler 4.1.4.4. KR FEC TX Gearbox 4.1.4.5. KR FEC RX Gearbox 4.1.4.6. Transcode Decoder
5. FEC in Intel® Stratix® 10 E-Tile Devices x
5.1. Types of RS-FEC 5.2. 100GBASE-KR4 5.3. 100GBASE-KP4 5.4. FEC Decoders 5.5. Specifications 5.6. Functions Within the RS-FEC Sublayer
5.1. Types of RS-FEC x
5.1.1. RS (528, 514, t = 7, m = 10) 5.1.2. RS (544, 514, t = 15, m = 10) 5.1.3. Supported RS-FEC Modes in E-Tile Devices
5.2. 100GBASE-KR4 x
5.2.1. 100GBASE-KR4 Mapping (IEEE802.3bj Clause 91)
5.3. 100GBASE-KP4 x
5.3.1. 100GBASE-KP4 Mapping (IEEE802.3bj Clause 91)
5.6. Functions Within the RS-FEC Sublayer x
5.6.1. Lane Block Synchronization 5.6.2. Alignment Lock and Deskew 5.6.3. Lane Re-order 5.6.4. Alignment Marker Removal 5.6.5. 64B/66B to 256B/257B Transcoder
7. FEC in Practical Application x
7.1. Datacenter Applications Scenario
8. Hardware Results x
8.1. Test Design 8.2. Test Setup 8.3. Insertion Loss Plots 8.4. FEC Statistics Tool 8.5. Hardware Data 8.6. Comparison to the Specification 8.7. References
1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction

8.5. Hardware Data

IL1 = Insertion loss point where corrected code words increase.

IL2 = Insertion loss point where uncorrected code words increase.

Total IL (dB) 1 Number of corrected bits Number of Corrected Symbols Number of Corrected Codewords Number of Uncorrected Codewords PRE-FEC BER 2 Estimated POST-FEC BER 2
38.7 0 0 0 0 0 0
44.3 2 2 2 0 6.48E-14 0
44.4 36 36 36 0 1.17E-12 0
44.8 91 91 91 0 2.95E-12 0
45.2 116 116 116 0 3.76E-12 0
45.8 418 418 418 0 1.35E-11 0
46.2 1131 1130 1130 0 3.66E-11 0
46.6 2469 2469 2469 0 7.99E-11 0
47 17984 17978 17978 0 5.83E-10 0
47.4 220808 220580 220519 0 7.13E-09 0
47.8 901459 899306 898544 0 2.91E-08 0
48.2 2567073 2557116 2551742 0 8.31E-08 0
48.6 6665926 6628124 6593734 0 2.15E-07 0
49 31511961 31252439 30527903 0 1.02E-06 0
49.2 113176637 111898208 103314714 0 3.66E-06 0
49.4 194993850 192151109 167763244 1 6.32E-06 2.72E-13
49.6 457728720 448886002 331518303 374 1.48E-05 1.02E-10
49.8 928669603 904545799 510475435 50083 3.00E-05 1.36E-08
1 Total IL = SI development kit loss + backplane loss + cable loss + variable ISI box loss.
2 BER values are estimates.
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