AN 846: Intel® Stratix® 10 Forward Error Correction

ID 683805
Date 7/02/2018
Public
Document Table of Contents

8.2. Test Setup

The test configuration included:

  • An Intel® Stratix® 10 TX signal integrity development kit board using the E-Tile device
  • FCI backplane (Megtron 6 material)
  • Variable ISI box

The FCI backplane is connected to the E-Tile device on one lane, starting with 28 dB loss (error free even without FEC). Attenuation is increased on only one channel using the variable ISI box. This provides fine control over the insertion loss.

Figure 30. Test Setup Board

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