E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

4.2.4. PMA Direct 25 Gbps x 4 (FEC Off)

This use case does not include FEC; therefore, there is no need for clock sharing between the four 25 Gbps channels.

For Core Interface FIFO in Phase Compensation mode, connect tx_clkout (402.832031 MHz) to tx_coreclkin and connect rx_clkout (402.832031 MHz) to rx_coreclkin. If you use any other source for tx_coreclkin or rx_coreclkin, make sure tx_coreclkin and rx_coreclkin have 0 PPM difference with the tx_clkout and rx_clkout, respectively. This example assumes that TX and RX Double Width transfer is enabled.

Figure 71. PMA Direct 25 Gbps x 4 (FEC Off)

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