Intel Agilex Device Data Sheet
Intel Agilex Device Data Sheet
Device Grade | Speed Grade Supported |
---|---|
Extended |
|
Industrial |
|
The suffix after the speed grade denotes the power options offered in Intel® Agilex™ devices.
- V—standard power (VID)
- E—lower power (VID)
- F—fixed voltage
Variant | Data Status |
---|---|
Intel® Agilex™ F-series | Advance |
Intel® Agilex™ I-series | Advance |
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Intel® Agilex™ devices.
Operating Conditions
Intel® Agilex™ devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel® Agilex™ devices, you must consider the operating requirements described in this section.
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for Intel® Agilex™ devices.
Recommended Operating Conditions
Symbol | Description | Condition | Minimum 1 | Typical | Maximum 1 | Unit |
---|---|---|---|---|---|---|
VCC | Core voltage power supply | –1V, –2V, –3V, –3E 2 | (Typical) – 3% | 0.685 – 0.85 3 | (Typical) + 3% | V |
–4F | 0.776 | 0.8 | 0.824 | V | ||
VCCP | Periphery circuitry power supply | –1V, –2V, –3V, –3E 2 | (Typical) – 3% | 0.685 – 0.85 3 | (Typical) + 3% | V |
–4F | 0.776 | 0.8 | 0.824 | V | ||
VCCPT | Power supply for programmable power technology and I/O pre-driver | — | 1.71 | 1.8 | 1.89 | V |
VCCH | Transceiver digital power supply | E-Tile and P-Tile devices | 0.87 | 0.9 | 0.93 | V |
VCCH_SDM | Secure Device Manager (SDM) block transceiver digital power supply | E-Tile and P-Tile devices | 0.87 | 0.9 | 0.93 | V |
VCCIO_PIO_SDM | SDM block I/O bank power supply | 1.5 V | 1.455 | 1.5 | 1.545 | V |
1.2 V | 1.14 | 1.2 | 1.26 | V | ||
VCCIO_SDM | SDM block configuration pins power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCL_SDM | SDM block core voltage power supply | — | 0.776 | 0.8 | 0.824 | V |
VCCFUSEWR_SDM | SDM block fuse writing power supply | — | 1.4 | — | 2.4 | V |
VCCPLLDIG_SDM | SDM block PLL digital power supply | — | 0.776 | 0.8 | 0.824 | V |
VCCPLL_SDM | SDM block PLL analog power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCBAT 4 | Battery back-up power supply (For design security volatile key register) | — | 1 | — | 1.8 | V |
VCCADC | ADC voltage sensor power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCIO_PIO | I/O bank power supply | 1.5 V | 1.455 | 1.5 | 1.545 | V |
1.2 V | 1.14 | 1.2 | 1.26 | V | ||
VCCA_PLL | PLL analog power supply | — | 1.71 | 1.8 | 1.89 | V |
VI 5 | DC input voltage | VCCIO_PIO = 1.2 V | –0.3 | — | 1.56 | V |
VCCIO_PIO = 1.5 V | –0.3 | — | 1.845 | V | ||
VCCIO_SDM, VCCIO_HPS = 1.8 V | –0.3 | — | 2.19 | V | ||
VO | Output voltage | — | 0 | — | VCCIO_PIO | V |
TJ | Operating junction temperature | Extended | 0 | — | 100 | °C |
Industrial | –40 | — | 100 | °C | ||
tRAMP 6 7 8 | Power supply ramp time | Standard POR | 200 μs | — | 100 ms | — |
Transceiver Power Supply Operating Conditions
Symbol | Description | Typical DC Level (V) | Recommended DC Setpoint (% of DC level) | Recommended VR Ripple (% of DC level) | Recommended AC Transient (% of DC level) | Maximum (DC Setpoint + Ripple + AC Transient) (% of DC level) |
---|---|---|---|---|---|---|
VCCRT_GXE 10 | Transceiver power supply | 0.9 | ± 0.5% | ± 2.5% | ± 3% | |
VCC_HSSI_GXE | E-tile digital signal power supply | 0.9 | ± 0.5% | ± 2.5% | ± 3% | |
VCCRTPLL_GXE 10 | Transceiver PLL power supply | 0.9 | ± 0.5% | ± 2.5% | ± 3% | |
VCCH_GXE | Analog power supply | 1.1 | ± 0.5% | ± 0.5% | ± 2% | ± 3% |
VCCCLK_GXE | LVPECL REFCLK power supply | 2.5 | ± 0.5% | ± 0.5% | ± 2% | ± 3% |
Symbol | Description | Typical DC Level (V) | Recommended DC Setpoint (% of DC level) | Recommended VR Ripple (% of DC level) | Recommended AC Transient (% of DC level) | Maximum (DC Setpoint + Ripple + AC Transient) (% of DC level) |
---|---|---|---|---|---|---|
VCCRT_GXP | Transceiver power supply | 0.9 | ± 0.5% | ± 2.5% | ± 3% | |
VCC_HSSI_GXP | P-tile digital signal power supply | 0.9 | ± 0.5% | ± 2.5% | ± 3% | |
VCCFUSE_GXP | P-tile efuse power supply | 0.9 | ± 0.5% | ± 2.5% | ± 3% | |
VCCCLK_GXP | P-tile I/O buffer power supply | 1.8 | ± 0.5% | ± 0.5% | ± 2% | ± 3% |
VCCH_GXP | High voltage power for Transceiver | 1.8 | ± 0.5% | ± 0.5% | ± 2% | ± 3% |
HPS Power Supply Operating Conditions
Symbol | Description | Condition | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|---|
VCCL_HPS | HPS core voltage and periphery circuitry power supply | Performance boost, fixed voltage: –1V | 0.87 | 0.9 | 0.93 | V |
SmartVID: –1V, –2V, –3V, –3E | 0.685 | — | 0.85 | V | ||
Fixed voltage: –4F | 0.776 | 0.8 | 0.824 | V | ||
VCCPLLDIG_HPS | HPS PLL digital power supply (can be connected to VCCL_HPS) | Performance boost, fixed voltage: –1V | 0.87 | 0.9 | 0.93 | V |
SmartVID: –1V, –2V, –3V, –3E | 0.685 | — | 0.85 | V | ||
Fixed voltage: –4F | 0.776 | 0.8 | 0.824 | V | ||
VCCPLL_HPS | HPS PLL analog power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |
VCCIO_HPS | HPS I/O buffers power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |
DC Characteristics
Supply Current and Power Consumption
Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer feature.
Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources.
The Intel® Quartus® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates.
I/O Pin Leakage Current
Symbol | Description | Condition | Min | Max | Unit |
---|---|---|---|---|---|
II | Input pin | VI = 0 V to VCCIO_PIO (MAX) | –250 | 250 | µA |
IOZ | Tri-stated I/O pin | VO = 0 V to VCCIO_PIO (MAX) | –250 | 250 | µA |
Bus Hold Specifications
The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Parameter | Symbol | Condition | VCCIO_PIO (V) | Unit | |
---|---|---|---|---|---|
1.2 | |||||
Min | Max | ||||
Bus-hold, low, sustaining current | ISUSL | VIN > VIL (max) | 30 | — | µA |
Bus-hold, high, sustaining current | ISUSH | VIN < VIH (min) | –30 | — | µA |
Bus-hold, low, overdrive current | IODL | 0 V < VIN < VCCIO_PIO | — | 1,200 | µA |
Bus-hold, high, overdrive current | IODH | 0 V < VIN < VCCIO_PIO | — | –1,200 | µA |
Bus-hold trip point | VTRIP | — | 0.3 | 0.9 | V |
OCT Calibration Accuracy Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block.
Symbol | Description | Condition (V) | Calibration Accuracy | Unit |
---|---|---|---|---|
34-Ω and 40-Ω RS | Internal series termination with calibration (34-Ω and 40-Ω setting) | VCCIO_PIO = 1.2 | ±15 | % |
50-Ω and 60-Ω RT | Internal parallel termination with calibration (50-Ω and 60-Ω setting) | SSTL-12 and HSTL-12 I/O standards | –10 to +60 | % |
POD12 I/O standard | ±15 |
OCT Without Calibration Resistance Tolerance Specifications
Symbol | Description | Condition (V) | Resistance Tolerance | Unit |
---|---|---|---|---|
34-Ω and 40-Ω RS | Internal series termination without calibration (34-Ω and 40-Ω setting) | VCCIO_PIO = 1.2 | –30 to +60 | % |
100-Ω RD | Internal differential termination (100-Ω setting) | VCCIO_PIO = 1.5 | ±40 | % |
Pin Capacitance
Internal Weak Pull-Up Resistor
All I/O pins, except configuration and JTAG pins, have an option to enable weak pull-up. For SDM and HPS, the configuration I/O and peripheral I/O are supported with weak pull-up and weak pull-down options.
Symbol | Description | Condition (V) | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
RPU | Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. | VCCIO_PIO = 1.2 ±5% | 3 | 10 | 30 | kΩ |
I/O Standard Specifications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Intel® Agilex™ devices.
For minimum voltage values, use the minimum VCCIO_PIO values. For maximum voltage values, use the maximum VCCIO_PIO values.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Single-Ended I/O Standards Specifications
I/O Standard | VCCIO_PIO(V) | VIL(V) | VIH(V) | ||||
---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | |
1.2 V LVCMOS | 1.14 | 1.2 | 1.26 | –0.3 | 0.35 × VCCIO_PIO | 0.65 × VCCIO_PIO | VCCIO_PIO + 0.3 |
Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
I/O Standard | VCCIO_PIO (V) | VREF (V) | VTT (V) | ||||||
---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | |
SSTL-12 | 1.14 | 1.2 | 1.26 | 0.49 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.51 × VCCIO_PIO | 0.475 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.525 × VCCIO_PIO |
HSTL-12 | 1.14 | 1.2 | 1.26 | 0.47 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.53 × VCCIO_PIO | 0.475 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.525 × VCCIO_PIO |
HSUL-12 | 1.14 | 1.2 | 1.26 | 0.49 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.51 × VCCIO_PIO | — | — | — |
POD12 | 1.14 | 1.2 | 1.26 | — | Internally calibrated | — | — | VCCIO_PIO | — |
Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
I/O Standard | VIL(DC) (V) | VIH(DC) (V) | VIL(AC) (V) | VIH(AC) (V) |
---|---|---|---|---|
Max | Min | Max | Min | |
SSTL-12 | VREF – 0.075 | VREF + 0.075 | VREF – 0.100 | VREF + 0.100 |
HSTL-12 | VREF – 0.080 | VREF + 0.080 | VREF – 0.150 | VREF + 0.150 |
HSUL-12 | VREF – 0.100 | VREF + 0.100 | VREF – 0.135 | VREF + 0.135 |
POD12 12 | VREF – 0.055 | VREF + 0.055 | VREF – 0.070 | VREF + 0.070 |
Differential SSTL, HSTL, and HSUL I/O Standards Specifications
I/O Standard | VCCIO_PIO (V) | VILdiff(DC) (V) | VIHdiff(DC) (V) | VILdiff(AC) (V) | VIHdiff(AC) (V) | VIX(AC) (V) | VOX(AC) (V) | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Max | Min | Max | Min | Min | Typ | Max | Min | Typ | Max | |
SSTL-12 | 1.14 | 1.2 | 1.26 | –0.15 | 0.15 | –0.2 | 0.2 | 0.5 × VCCIO_PIO – 0.12 | 0.5 × VCCIO_PIO | 0.5 × VCCIO_PIO + 0.12 | 0.5 × VCCIO_PIO – 0.12 | 0.5 × VCCIO_PIO | 0.5 × VCCIO_PIO + 0.12 |
HSTL-12 | 1.14 | 1.2 | 1.26 | –0.16 | 0.16 | –0.3 | 0.3 | 0.5 × VCCIO_PIO – 0.12 | 0.5 × VCCIO_PIO | 0.5 × VCCIO_PIO + 0.12 | 0.5 × VCCIO_PIO – 0.12 | 0.5 × VCCIO_PIO | 0.5 × VCCIO_PIO + 0.12 |
HSUL-12 | 1.14 | 1.2 | 1.26 | –0.2 | 0.2 | –0.27 | 0.27 | 0.5 × VCCIO_PIO – 0.12 | 0.5 × VCCIO_PIO | 0.5 × VCCIO_PIO + 0.12 | 0.5 × VCCIO_PIO – 0.12 | 0.5 × VCCIO_PIO | 0.5 × VCCIO_PIO + 0.12 |
Differential POD I/O Standards Specifications
I/O Standard | VCCIO_PIO (V) | VILdiff(DC) (V) | VIHdiff(DC) (V) | VILdiff(AC) (V) | VIHdiff(AC) (V) | VIX(AC) (%) 13 | ||
---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Max | Min | Max | Min | Max | |
POD12 | 1.14 | 1.2 | 1.26 | –0.11 | 0.11 | –0.14 | 0.14 | 25 |
Differential I/O Standards Specifications
I/O Standard | VCCIO_PIO (V) | VID (mV) 14 | VICM(DC) (V) | VOD (V) 15 16 | VOCM (V) 15 | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Min | Condition | Max | Min | Typ | Max | Min | Typ | Max | |
1.5 V True Differential Signaling 17 | 1.455 | 1.5 | 1.545 | 100 | 0.3 | Data rate ≤700 Mbps | 1.4 | 0.247 | — | 0.454 | 0.99 | 1.1 | 1.21 |
1 | Data rate >700 Mbps | 1.4 |
Switching Characteristics
This section provides the performance characteristics of Intel® Agilex™ core and periphery blocks.
Core Performance Specifications
Clock Tree Specifications
Parameter | Performance | Unit | ||
---|---|---|---|---|
–1V | –2V | –3V, –3E, –4F | ||
Programmable clock routing | 1,100 | 1,000 | 780 | MHz |
I/O PLL Specifications
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN | Input clock frequency | –1V | 10 | — | 1,100 18 | MHz |
–2V | 10 | — | 900 18 | MHz | ||
–3V, –3E, –4F | 10 | — | 750 18 | MHz | ||
fINPFD | Input clock frequency to the PFD | — | 10 | — | 325 | MHz |
fVCO | I/O PLL VCO operating range | –1V | 600 | — | 1,600 | MHz |
–2V | 600 | — | 1,434 | MHz | ||
–3V, –3E, –4F | 600 | — | 1,250 | MHz | ||
fCLBW | I/O PLL closed-loop bandwidth | I/O bank I/O PLL | 0.5 | — | 10 | MHz |
Fabric-feeding I/O PLL | 1 | — | 10 | MHz | ||
tEINDUTY | Input clock or external feedback clock input duty cycle | — | 40 | — | 60 | % |
fOUT | Output frequency for internal clock (C counter) | –1V | — | — | 1,100 | MHz |
–2V | — | — | 900 | MHz | ||
–3V, –3E, –4F | — | — | 750 | MHz | ||
fOUT_EXT | Output frequency for external clock output | –1V | — | — | 800 | MHz |
–2V | — | — | 720 | MHz | ||
–3V, –3E, –4F | — | — | 650 | MHz | ||
tOUTDUTY | Duty cycle for dedicated external clock output (when set to 50%) | — | 45 | 50 | 55 | % |
tFCOMP | External feedback clock compensation time | — | — | — | 5 | ns |
fDYCONFIGCLK | Dynamic configuration clock for mgmt_clk and scanclk | — | — | — | 200 | MHz |
tLOCK | Time required to lock from end-of-device configuration or deassertion of areset | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
tPLL_PSERR | Accuracy of PLL phase shift | — | — | — | ±50 | ps |
tARESET | Minimum pulse width on the areset signal | — | 10 | — | — | ns |
tINCCJ 19 20 | Input clock cycle-to-cycle jitter | fREF < 100 MHz | — | — | ±750 | ps |
fREF ≥ 100 MHz | — | — | 0.15 | UI | ||
tOUTPJ_DC | Period jitter for dedicated clock output | fREF < 100 MHz | — | — | 175 | ps |
fREF ≥ 100 MHz | — | — | 17.5 | mUI | ||
tOUTCCJ_DC | Cycle-to-cycle jitter for dedicated clock output | fREF < 100 MHz | — | — | 175 | ps |
fREF ≥ 100 MHz | — | — | 17.5 | mUI | ||
tOUTPJ_IO 21 | Period jitter for clock output on the regular I/O | fREF < 100 MHz | — | — | 600 | ps |
fREF ≥ 100 MHz | — | — | 60 | mUI | ||
tOUTCCJ_IO 21 | Cycle-to-cycle jitter for clock output on the regular I/O | fREF < 100 MHz | — | — | 600 | ps |
fREF ≥ 100 MHz | — | — | 60 | mUI | ||
tCASC_OUTPJ_DC 22 | Period jitter for dedicated clock output in cascaded PLLs | fREF < 100 MHz | — | — | 175 | ps |
fREF ≥ 100 MHz | — | — | 17.5 | mUI |
DSP Block Specifications
Mode | Performance | Unit | |||
---|---|---|---|---|---|
–1V | –2V | –3V, –3E | –4F | ||
Fixed-point 18 × 19 multiplication mode | 900 | 771 | 676 | 600 | MHz |
Fixed-point 27 × 27 multiplication mode | 900 | 771 | 676 | 600 | MHz |
Fixed-point 18 × 19 multiplier adder mode 23 | 900 | 771 | 676 | 600 | MHz |
Fixed-point 18 × 19 multiplier adder summed with 36-bit input mode | 900 | 771 | 676 | 600 | MHz |
Fixed-point 18 × 19 systolic mode | 900 | 771 | 676 | 600 | MHz |
Fixed-point 18 × 19 complex multiplication mode | 900 | 771 | 676 | 600 | MHz |
Fixed-point four 9 × 9 multiplier adder mode 23 | 900 | 771 | 676 | 600 | MHz |
FP32 floating-point multiplication mode | 750 | 579 | 507 | 475 | MHz |
FP32 floating-point adder or subtract mode | 750 | 579 | 507 | 475 | MHz |
FP32 floating-point multiplier adder or subtract mode | 750 | 579 | 507 | 475 | MHz |
FP32 floating-point multiplier accumulate mode | 750 | 579 | 507 | 475 | MHz |
Addition or subtraction of two FP16 floating-point multiplication mode | 750 | 579 | 507 | 475 | MHz |
FP32 floating-point complex multiplication | 750 | 579 | 507 | 475 | MHz |
FP32 floating-point direct vector dot product | 750 | 579 | 507 | 475 | MHz |
FP16 floating-point complex multiplication | 750 | 579 | 507 | 475 | MHz |
FP16 floating-point direct vector dot product | 750 | 579 | 507 | 475 | MHz |
- –1V: 675 MHz
- –2V: 578 MHz
- –3V and –3E: 507 MHz
- –4F: 450 MHz
Memory Block Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel® Quartus® Prime software to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
Memory | Mode | Performance | Unit | |||
---|---|---|---|---|---|---|
–1V | –2V | –3V, –3E | –4F | |||
MLAB | Single port, all supported widths (×16/×32) | 1,000 | 782 | 667 | 600 | MHz |
Simple dual-port, all supported widths (×16/×32) | 1,000 | 782 | 667 | 600 | MHz | |
Simple dual-port with read-during-write option | 600 | 500 | 420 | 360 | MHz | |
ROM, all supported width (×16/×32) | 1,000 | 782 | 667 | 600 | MHz | |
M20K Block | Single-port, all supported widths | 1,000 | 782 | 667 | 600 | MHz |
Simple dual-port, all supported widths | 1,000 | 782 | 667 | 600 | MHz | |
Simple dual-port, coherent read enabled | 1,000 | 782 | 667 | 600 | MHz | |
Simple dual-port with the read-during-write option set to Old Data, all supported widths | 800 | 640 | 560 | 480 | MHz | |
Simple dual-port with ECC enabled, 512 × 32 | 600 | 500 | 420 | 310 | MHz | |
Simple dual-port with ECC, optional pipeline registers enabled, 512 × 32 | 1,000 | 782 | 667 | 450 | MHz | |
True dual port, all supported widths | 600 | 500 | 420 | 340 | MHz | |
Simple quad-port, all supported widths | 600 | 500 | 420 | 340 | MHz | |
ROM, all supported widths | 1,000 | 782 | 667 | 600 | MHz | |
eSRAM | Simple dual-port | 750 | 640 | 500 | 500 | MHz |
Local Temperature Sensor Specifications
Remote Temperature Diode Specifications
Note the following for the remote temperature diode specifications:
- The typical value is at 25°C.
- Diode accuracy improves with lower injection current.
- Absolute accuracy is dependent on third-party external diode ADC and integration specifics.
Description | Min | Typ | Max | Unit |
---|---|---|---|---|
Ibias, diode source current | 25 | — | 25 | μA |
Vbias, voltage across diode | 25 | — | 25 | V |
Series resistance | — | — | 25 | Ω |
Diode ideality factor | — | 25 | — | — |
Description | Min | Typ | Max | Unit |
---|---|---|---|---|
Ibias, diode source current | 100 | — | 170 | μA |
Vbias, voltage across diode | 0.56 | — | 0.8 | V |
Series resistance | — | — | < 2 | Ω |
Diode ideality factor | — | 1.008 | — | — |
Voltage Sensor Specifications
Parameter | Minimum | Typical | Maximum | Unit | |
---|---|---|---|---|---|
Resolution | — | 7 | — | Bit | |
Sampling rate | — | — | 1 | KSPS | |
Differential non-linearity (DNL) | — | — | ±1 | LSB | |
Integral non-linearity (INL) | — | — | ±1 | LSB | |
Input capacitance | — | — | 40 | pF | |
Voltage sensor accuracy, Vin range: 0 V to 1.249 V | –3.5 | — | 3.5 | % | |
Unipolar Input Mode | Input signal range for Vsigp | 0 | — | 1.49 | V |
Common mode voltage on Vsign | 0 | — | 0.25 | V | |
Input signal range for Vsigp – Vsign | 0 | — | 1.24 | V |
Periphery Performance Specifications
This section describes the periphery performance, LVDS SERDES, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
LVDS SERDES Specifications
Symbol | Condition | –1 Speed Grade | –2 Speed Grade | –3 Speed Grade | –4 Speed Grade | Unit | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK_in (input clock frequency) True Differential I/O Standards | Clock boost factor W = 1 to 40 26 | 10 | — | 800 | 10 | — | 700 | 10 | — | 625 | 10 | — | 625 | MHz | |
fHSCLK_in (input clock frequency) Single-Ended I/O Standards | Clock boost factor W = 1 to 40 26 | 10 | — | 625 | 10 | — | 625 | 10 | — | 525 | 10 | — | 525 | MHz | |
fHSCLK_OUT (output clock frequency) | — | — | — | 800 27 | — | — | 700 27 | — | — | 625 27 | — | — | 625 27 | MHz | |
Transmitter | True Differential I/O Standards - fHSDR (data rate) 28 | SERDES factor J = 4 to 10 29 30 31 | 150 | — | 1,600 | 150 | — | 1,434 | 150 | — | 1,250 | 150 | — | 1,000 | Mbps |
SERDES factor J = 3 29 30 31 | 150 | — | 1,200 | 150 | — | 1,076 | 150 | — | 938 | 150 | — | 600 | Mbps | ||
SERDES factor J = 2, uses DDR registers | 150 | — | 840 32 | 150 | — | 32 | 150 | — | 32 | 150 | — | 32 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 150 | — | 420 32 | 150 | — | 32 | 150 | — | 32 | 150 | — | 32 | Mbps | ||
tx Jitter - True Differential I/O Standards | Total jitter for data rate, 600 Mbps – 1.6 Gbps | — | — | 160 | — | — | 200 | — | — | 250 | — | — | 250 | ps | |
Total jitter for data rate, < 600 Mbps | — | — | 0.1 | — | — | 0.12 | — | — | 0.15 | — | — | 0.15 | UI | ||
tDUTY 33 | TX output clock duty cycle for Differential I/O Standards | 45 | 50 | 55 | 45 | 50 | 55 | 45 | 50 | 55 | 45 | 50 | 55 | % | |
tRISE & tFALL 30 34 | True Differential I/O Standards | — | — | 160 | — | — | 180 | — | — | 200 | — | — | 220 | ps | |
TCCS 28 33 | True Differential I/O Standards | — | — | 330 | — | — | 330 | — | — | 330 | — | — | 330 | ps | |
Receiver | True Differential I/O Standards - fHSDRDPA (data rate) | SERDES factor J = 4 to 10 29 30 31 | 150 | — | 1,600 | 150 | — | 1,434 | 150 | — | 1,250 | 150 | — | 1,000 | Mbps |
SERDES factor J = 3 29 30 31 | 150 | — | 1,200 | 150 | — | 1,076 | 150 | — | 938 | 150 | — | 600 | Mbps | ||
fHSDR (data rate) (without DPA) 28 | SERDES factor J = 3 to 10 | 31 | — | 35 | 31 | — | 35 | 31 | — | 35 | 31 | — | 35 | Mbps | |
SERDES factor J = 2, uses DDR registers | 31 | — | 32 | 31 | — | 32 | 31 | — | 32 | 31 | — | 32 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 31 | — | 32 | 31 | — | 32 | 31 | — | 32 | 31 | — | 32 | Mbps | ||
DPA (FIFO mode) | DPA run length | — | — | — | 10,000 | — | — | 10,000 | — | — | 10,000 | — | — | 10,000 | UI |
DPA (soft CDR mode) | DPA run length | SGMII/GbE protocol | — | — | 5 | — | — | 5 | — | — | 5 | — | — | 5 | UI |
All other protocols | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | ||
Soft CDR mode | Soft-CDR ppm tolerance | — | –300 | — | 300 | –300 | — | 300 | –300 | — | 300 | –300 | — | 300 | ppm |
Non DPA mode | Sampling Window | — | — | — | 330 | — | — | 330 | — | — | 330 | — | — | 330 | ps |
DPA Lock Time Specifications
Standard | Training Pattern | Number of Data Transitions in One Repetition of the Training Pattern | Number of Repetitions per 256 Data Transitions 36 | Maximum Data Transition |
---|---|---|---|---|
SPI-4 | 00000000001111111111 | 2 | 128 | 960 |
Parallel Rapid I/O | 00001111 | 2 | 128 | 960 |
10010000 | 4 | 64 | 960 | |
Miscellaneous | 10101010 | 8 | 32 | 960 |
01010101 | 8 | 32 | 960 |
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Jitter Frequency (Hz) | Sinusoidal Jitter (UI) | |
---|---|---|
F1 | 10,000 | 25.00 |
F2 | 17,565 | 25.00 |
F3 | 1,493,000 | 0.28 |
F4 | 50,000,000 | 0.28 |
Memory Standards Supported by the Hard Memory Controller
Memory Standard | Rate Support | Maximum Frequency (MHz) |
---|---|---|
DDR4 SDRAM | Quarter rate | 1,600 |
Memory Standards Supported by the Soft Memory Controller
Memory Standard | Rate Support | Maximum Frequency (MHz) |
---|---|---|
RLDRAM 3 37 | Quarter rate | 1,200 |
QDR IV SRAM | Quarter rate | 1,066 |
Memory Standards Supported by the HPS Hard Memory Controller
Memory Standard | Rate Support | Maximum Frequency (MHz) |
---|---|---|
DDR4 SDRAM | Quarter rate | 1,600 |
Half rate | 1,333 |
DLL Range Specifications
Parameter | Performance (for All Speed Grades) | Unit |
---|---|---|
DLL operating frequency range | 600 – 1,600 | MHz |
DLL reference clock input | Minimum 600 | MHz |
Memory Output Clock Jitter Specifications
The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks for better jitter performance.
The memory clock output jitter is within the JEDEC specifications with an input of 10 ps peak-to-peak jitter.
E-Tile Transceiver Performance Specifications
This section provides E-tile transceiver specifications and timing for Intel® Agilex™ devices.
Transceiver Performance for E-Tile Devices
Transceiver Reference Clock Specifications
Symbol | Refclk Parameter | Min | Typ | Max | Unit |
---|---|---|---|---|---|
VTT | Termination Voltage (2.5V compliant) | 0.4 | 0.5 | 0.6 | V |
VTT | Termination Voltage (3.3V compliant) | 1.04 | 1.3 | 1.56 | V |
RTT | Termination Resistor | 40 | 50 | 60 | Ω |
VDIFF | Differential Voltage | 0.4 | 0.8 | 1.2 | V |
VCM | Input Common Mode Voltage (2.5V compliant, no internal termination resistor) | VDIFF/2 | — | VCCCLK_GXE-VDIFF/2 | V |
VCM | Input Common Mode Voltage (2.5V compliant, internal termination resistor) | VCCCLK_GXE - 1.6 | VCCCLK_GXE - 1.3 | VCCCLK_GXE - 1.0 | V |
VCM | Input Common Mode Voltage (3.3V compliant, no internal termination resistor) | VDIFF/2 | — | VCCCLK_GXE-VDIFF/2 | V |
VCM | Input Common Mode Voltage (3.3V compliant, internal termination resistor) | 1.4 | 2 | 2.6 | V |
Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Frequency | — | 125 | 156.25 | 700 | MHz |
Frequency Tolerance | — | -100 | — | 100 | PPM |
Clock Duty Cycle | — | 45 | 50 | 55 | % |
Rise & Fall Times | 20% to 80% | 40 | — | 300 | ps |
Phase Jitter | 12 kHz to 20 MHz | — | 0.375 | 0.5 | ps rms |
Phase Noise 40 | 10 kHz | — | — | -130 | dBc/Hz |
100 kHz | — | — | -138 | dBc/Hz | |
500 kHz | — | — | -138 | dBc/Hz | |
3 MHz | — | — | -140 | dBc/Hz | |
10 MHz | — | — | -144 | dBc/Hz | |
20 MHz | — | — | -146 | dBc/Hz |
Transmitter Specifications for E-Tile Devices
Symbol/Description | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Transmitter differential output voltage peak-to-peak | No precursor/postcursor de-emphasis | — | 0.97 | — | V |
Transmitter common mode voltage | — | VCCRT_GXE/2 | V |
Receiver Specifications for E-Tile Devices
Symbol/Description | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Receiver run length41 | — | — | — | 10042 | symbols |
DC input impedance | — | 40 | — | 60 | Ω |
DC differential input impedance | — | 80 | 100 | 120 | Ω |
Powered down DC input impedance | Receiver pin impedance when the receiver termination is powered down | 100k | — | — | Ω |
Electrical Idle detection voltage | — | 65 | — | 175 | mV |
Differential termination | From DC to 100 MHz | 80 | 100 | 120 | Ω |
PPM tolerance | Allowed frequency mismatch between REFCLK and RX data | — | — | 750 | ppm |
P-Tile Transceiver Performance Specifications
This section provides P-tile transceiver specifications and timing for Intel® Agilex™ devices.
Transceiver Performance for P-Tile Devices
Symbol/Description | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Supported data rate | Chip-to-chip and Backplane | 2.5 | — | 16 | Gbps |
Symbol/Description | Condition | Transceiver Speed Grade | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
VCO frequency | — | — | — | 5 | GHz |
PLL bandwidth (BWTX-PKG_PLL1) | PCIe 2.5 GT/s | 1.5 | — | 22 | MHz |
PLL peaking (PKGTX-PLL1) | PCIe 2.5 GT/s | — | — | 3 | dB |
PLL bandwidth (BWTX-PKG_PLL2) | PCIe 5.0 GT/s | 5 | — | 16 | MHz |
PLL peaking (PKGTX-PLL2) | PCIe 5.0 GT/s | — | — | 1 | dB |
Symbol/Description | Condition | Transceiver Speed Grade | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
VCO frequency | — | — | — | 8 | GHz |
PLL bandwidth (BWTX-PKG_PLL1) | PCIe 8.0 GT/s | 2 | — | 4 | MHz |
PCIe 16.0 GT/s | 2 | — | 4 | MHz | |
PLL peaking (PKGTX-PLL1) | PCIe 8.0 GT/s | — | — | 2 | dB |
PCIe 16.0 GT/s | — | — | 2 | dB |
Transceiver Reference Clock Specifications
Symbol/Description | Condition | All Transceiver Speed Grades | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | HCSL | — | ||
Input Reference Clock Frequency43 | — | 99.97 | 100 | 100.03 | MHz |
Rising Edge Rate 44 | — | 0.6 | — | 4 | V/ns |
Falling Edge Rate44 | — | 0.6 | — | 4 | V/ns |
Duty cycle | — | 40 | — | 60 | % |
Spread-spectrum modulating clock frequency | — | 30 | — | 33 | kHz |
Spread-spectrum downspread | — | — | 0 to -0.5 | — | % |
Absolute VMAX | — | — | 1.15 | — | V |
Absolute VMIN | — | — | -0.3 | — | V |
Peak-to-peak differential input voltage | — | 300 | — | 1500 | mV |
VICM (DC coupled) | — | 250 | — | 550 | mV |
Cycle to cycle jitter (TCCJITTER) 45 | — | — | — | 150 | ps |
TSSC-MAX-PERIOD-SLEW | — | — | — | 1250 | ppm/us |
Transmitter Specification for P-Tile Devices
Symbol/Description | Condition | All Transceiver Speed Grades | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O | — | ||
Differential on-chip termination resistors | — | 80 | — | 120 | Ω |
Differential peak-to-peak voltage for full swing | PCIe 2.5 GT/s | 800 | — | 1100 | mV |
PCIe 5.0 GT/s | 800 | — | 1100 | mV | |
PCIe 8.0 GT/s | 800 | — | 1100 | mV | |
PCIe 16.0 GT/s | 800 | — | 1100 | mV | |
Differential peak-to-peak voltage for reduced swing | PCIe 2.5 GT/s | 400 | — | 1100 | mV |
PCIe 5.0 GT/s | 400 | — | 1100 | mV | |
PCIe 8.0 GT/s | 400 | — | 1100 | mV | |
PCIe 16.0 GT/s | 400 | — | 1100 | mV | |
Differential peak-to-peak voltage during EIEOS | PCIe 8.0 GT/s and 16.0 GT/s | 250 | — | — | mV |
Differential peak-to-peak voltage during EIEOS for reduce swing | PCIe 8.0 GT/s and 16.0 GT/s | 232 | — | — | mV |
VOCM (AC coupled) | — | 0 | — | 360 | mV |
Lane-to-lane output skew | PCIe 2.5 GT/s | — | — | 2.5 | ns |
PCIe 5.0 GT/s | — | — | 2 | ns | |
PCIe 8.0 GT/s | — | — | 1.5 | ns | |
PCIe 16.0 GT/s | — | — | 1.25 | ns |
Receiver Specifications for P-Tile Devices
Symbol/Description | Condition | All Transceiver Speed Grades | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O | |||
Peak-to-peak differential input voltage VID (diff p-p) | PCIe 2.5 GT/s46 | 0.175 | — | 1.2 | V |
PCIe 5.0 GT/s46 | 0.1 | — | 1.2 | V | |
VICM (AC coupled) | — | — | 0 | — | V |
Differential on-chip termination resistors | — | 80 | — | 120 | Ω |
RESREF | — | 198 | 200 | 202 | Ω |
HPS Performance Specifications
This section provides hard processor system (HPS) specifications and timing for Intel® Agilex™ devices.
HPS Clock Performance
Performance | VCCL_HPS (V) | MPU Frequency (MHz) | L3 Frequency (MHz) (l3_main_free_clk) | MPFE Frequency (MHz) | Rate | DDR Clock (MHz) | DDR (Mb/s per pin) |
---|---|---|---|---|---|---|---|
–1 speed grade | Fixed: 0.9 | 1,410 | 400 | 400 | Quarter | 1,600 | 3,200 |
600 | Half | 1,200 | 2,400 | ||||
SmartVID | 1,350 | 400 | 366.625 | Quarter | 1,466.5 | 2,933 | |
600 | Half | 1,200 | 2,400 | ||||
–2 speed grade | SmartVID | 1,200 | 400 | 300 | Quarter | 1,200 | 2,400 |
600 | Half | 1,200 | 2,400 | ||||
533.25 | Half | 1,066.5 | 2,133 | ||||
–3 speed grade | SmartVID | 1,000 | 400 | 466.5 | Half | 933 | 1,866 |
400 | Half | 800 | 1,600 | ||||
–4 speed grade | Fixed: 0.8 | 800 | 400 | TBD | TBD | TBD | TBD |
HPS Internal Oscillator Frequency
Description | Min | Typ | Max | Unit |
---|---|---|---|---|
Internal Oscillator Frequency | 160 | 370 | 400 | MHz |
HPS PLL Specifications
HPS PLL Input Requirements
Description | Min | Typ | Max | Unit |
---|---|---|---|---|
Clock input range | 25 | — | 125 | MHz |
Clock input accuracy | — | — | 50 | PPM |
Clock input duty cycle | 45 | 50 | 55 | % |
HPS PLL Performance
HPS SPI Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tspi_ref_clk | The period of the SPI internal reference clock, sourced from l4_main_clk | 2.5 | — | — | ns |
Tclk | SPIM_CLK clock period | 16.67 | — | — | ns |
Tdutycycle | SPIM_CLK duty cycle | 45 | 50 | 55 | % |
Tck_jitter | SPIM_CLK output jitter | — | — | 2 | % |
Tdio | Master-out slave-in (MOSI) output skew | –3 | — | 2 | ns |
Tdssfrst 48 | SPI_SS_N asserted to first SPIM_CLK edge | (1.5 × Tclk) – 2 | — | — | ns |
Tdsslst 48 | Last SPIM_CLK edge to SPI_SS_N deasserted | Tclk – 2 | — | — | ns |
Tsu 49 | SPIM_MISO setup time with respect to SPIM_CLK capture edge | 4 .5 – ( rx_sample_dly × T spi_ref_clk ) 50 | — | — | ns |
Th 49 | Input hold in respect to SPIM_CLK capture edge | 1.3 + (rx_sample_dly× Tspi_ref_clk) | — | — | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tspi_ref_clk | The period of the SPI internal reference clock, sourced from l4_main_clk | 2.5 | — | — | ns |
Tclk | SPIM_CLK clock period | 30 | — | — | ns |
Tdutycycle | SPIM_CLK duty cycle | 45 | 50 | 55 | % |
Td | Master-in slave-out (MISO) output skew | (2 × Tspi_ref_clk) + 3 | — | (3 × Tspi_ref_clk) + 11 | ns |
Tsu | Master-out slave-in (MOSI) setup time | 4 | — | — | ns |
Th | Master-out slave-in (MOSI) hold time | 9 | — | — | ns |
Tsuss | SPI_SS_N asserted to first SPIM_CLK edge | Tspi_ref_clk + 4 | — | — | ns |
Thss | Last SPIM_CLK edge to SPI_SS_N deasserted | Tspi_ref_clk + 4 | — | — | ns |
HPS SD/MMC Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tsdmmc_cclk | SDMMC_CCLK clock period (Identification mode) | 2500 | — | — | ns |
SDMMC_CCLK clock period (SDR12) | 40 | — | — | ns | |
SDMMC_CCLK clock period (SDR25) | 20 | — | — | ns | |
Tdutycycle | SDMMC_CCLK duty cycle | 45 | 50 | 55 | % |
Tsdmmc_cclk_jitter | SDMMC_CCLK output jitter | — | — | 2 | % |
Tsdmmc_clk | Internal reference clock before division by 4 | 5 | — | — | ns |
Td | SDMMC_CMD/SDMMC_DATA[7:0] output delay 51 | Tsdmmc_clk × drvsel/2 | — | 3 + (Tsdmmc_clk × drvsel/2) | ns |
Tsu | SDMMC_CMD/SDMMC_DATA[7:0] input setup 52 | 6 – (Tsdmmc_clk × smplsel/2) | — | — | ns |
Th | SDMMC_CMD/SDMMC_DATA[7:0] input hold 52 | 0.5 + (Tsdmmc_clk × smplsel/2) | — | — | ns |
None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at 1.8 V at power on.
HPS USB UPLI Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tusb_clk | USB_CLK clock period | — | 16.667 | — | ns |
Td | Clock to USB_STP/USB_DATA[7:0] output delay | 2 | — | 7 | ns |
Tsu | Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] | 4 | — | — | ns |
Th | Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] | 1 | — | — | ns |
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk (1000Base-T) | TX_CLK clock period | — | 8 | — | ns |
Tclk (100Base-T) | TX_CLK clock period | — | 40 | — | ns |
Tclk (10Base-T) | TX_CLK clock period | — | 400 | — | ns |
Tdutycycle (1000Base-T) | TX_CLK duty cycle | 45 | 50 | 55 | % |
Tdutycycle(10/100Base-T) | TX_CLK duty cycle | 40 | 50 | 60 | % |
Td 53 |
TXD/TX_CTL to TX_CLK output skew | –0.5 | — | 0.5 | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk (1000Base-T) | RX_CLK clock period | — | 8 | — | ns |
Tclk (100Base-T) | RX_CLK clock period | — | 40 | — | ns |
Tclk (10Base-T) | RX_CLK clock period | — | 400 | — | ns |
Tdutycycle(1000Base-T) | RX_CLK duty cycle | 45 | 50 | 55 | % |
Tdutycycle(10/100Base-T) | RX_CLK duty cycle | 40 | 50 | 60 | % |
Tsu | RX_D/RX_CTL to RX_CLK setup time | 1 | — | — | ns |
Th 55 | RX_CLK to RX_D/RX_CTL hold time | 1 | — | — | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | REF_CLK clock period, sourced by HPS TX_CLK | — | 20 | — | ns |
REF_CLK clock period, sourced by external clock source | — | 20 | — | ns | |
Tdutycycle_int | Clock duty cycle, REF_CLK sourced by TX_CLK | 35 | 50 | 65 | % |
Tdutycycle_ext | Clock duty cycle, REF_CLK sourced by external clock source | 35 | 50 | 65 | % |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Td | TX_CLK to TXD/TX_CTL output data delay | 2 | — | 10 | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tsu | RX_D/RX_CTL setup time | 2 | — | — | ns |
Th | RX_D/RX_CTL hold time | 1 | — | — | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | MDC clock period | 400 | — | — | ns |
Td | MDC to MDIO output data delay | 10 | — | 300 | ns |
Tsu | Setup time for MDIO data | 10 | — | — | ns |
Th | Hold time for MDIO data | 0 | — | — | ns |
If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK by 1.5-2 ns, using the HPS I/O programmable delay.
HPS I2C Timing Characteristics
Symbol | Description | Standard Mode | Fast Mode | Unit | ||
---|---|---|---|---|---|---|
Min | Max | Min | Max | |||
Tclk | Serial clock (SCL) clock period | 10 | — | 2.5 | — | μs |
Tclk_jitter | I2C clock output jitter | — | 2 | — | 2 | % |
THIGH 56 | SCL high period | 4 57 | — | 0.6 58 | — | μs |
TLOW 59 | SCL low period | 4.7 60 | — | 1.3 61 | — | μs |
TSU;DAT | Setup time for serial data line (SDA) data to SCL | 0.25 | — | 0.1 | — | μs |
THD;DAT 62 | Hold time for SCL to SDA data | 0 | 3.15 | 0 | 0.6 | μs |
TVD;DAT and TVD;ACK 63 | SCL to SDA output data delay | — | 3.45 64 | — | 0.9 65 | μs |
TSU;STA | Setup time for a repeated start condition | 4.7 | — | 0.6 | — | μs |
THD;STA | Hold time for a repeated start condition | 4 | — | 0.6 | — | μs |
TSU;STO | Setup time for a stop condition | 4 | — | 0.6 | — | μs |
TBUF | SDA high pulse duration between STOP and START | 4.7 | — | 1.3 | — | μs |
Tscl:r 66 | SCL rise time | — | 1000 | 20 | 300 | ns |
Tscl:f 66 | SCL fall time | — | 300 | 6.54 | 300 | ns |
Tsda:r 66 | SDA rise time | — | 1000 | 20 | 300 | ns |
Tsda:f 66 | SDA fall time | — | 300 | 6.54 | 300 | ns |
HPS NAND Timing Characteristics
Symbol | Description | Min | Max | Unit |
---|---|---|---|---|
TWP 67 | Write enable pulse width | 10 | — | ns |
TWH 67 | Write enable hold time | 7 | — | ns |
TRP 67 | Read enable pulse width | 10 | — | ns |
TREH 67 | Read enable hold time | 7 | — | ns |
TCLS 67 | Command latch enable to write enable setup time | 10 | — | ns |
TCLH 67 | Command latch enable to write enable hold time | 5 | — | ns |
TCS 67 | Chip enable to write enable setup time | 15 | — | ns |
TCH 67 | Chip enable to write enable hold time | 5 | — | ns |
TALS 67 | Address latch enable to write enable setup time | 10 | — | ns |
TALH 67 | Address latch enable to write enable hold time | 5 | — | ns |
TDS 67 | Data to write enable setup time | 7 | — | ns |
TDH 67 | Data to write enable hold time | 5 | — | ns |
TWB 67 | Write enable high to R/B low | — | 200 | ns |
TCEA | Chip enable to data access time | — | 100 | ns |
TREA | Read enable to data access time | — | 40 | ns |
TRHZ | Read enable to data high impedance | — | 200 | ns |
TRR | Ready to read enable low | 20 | — | ns |
HPS Trace Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | Trace clock period | 6.667 | — | — | ns |
Tclk_jitter | Trace clock output jitter | — | — | 2 | % |
Tdutycycle | Trace clock maximum duty cycle | 45 | 50 | 55 | % |
Td | Tclk to D0–D15 output data delay | 0 | — | 1.8 | ns |
HPS GPIO Interface
The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is 1 debounce clock cycle and the minimum detectable GPIO pulse width is 62.5 µs (at 32 kHz).
If the external signal is driven into the GPIO for less than one clock cycle, the external signal is filtered. If the external signal is between one and two clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If the external signal is more than two clock cycles, the external signal is not filtered.
HPS JTAG Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
tJCP | TCK clock period | 41.66 | — | — | ns |
tJCH | TCK clock high time | 20 | — | — | ns |
tJCL | TCK clock low time | 20 | — | — | ns |
tJPSU (TDI) | TDI JTAG port setup time | 5 | — | — | ns |
tJPSU (TMS) | TMS JTAG port setup time | 5 | — | — | ns |
tJPH | JTAG port hold time | 0 | — | — | ns |
tJPCO | JTAG port clock to output | 0 | — | 8 | ns |
tJPZX | JTAG port high impedance to valid output | — | — | 10 | ns |
tJPXZ | JTAG port valid output to high impedance | — | — | 10 | ns |
HPS Programmable I/O Timing Characteristics
output_val_en | output_val | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
0 | — | No I/O delay enabled | TBD | 0 | TBD | ps |
1 | [0:31] | Intrinsic I/O delay + 1×Minimum + output_val × Chain Delay | TBD | TBD | TBD | ps |
2 (INVALID) | — | — | — | — | — | — |
3 | [0:31] | Intrinsic I/O delay + 2×Minimum + output_val × Chain Delay | TBD | TBD | TBD | ps |
input_val_en | input_val | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
0 | — | No I/O delay enabled | TBD | 0 | TBD | ps |
1 | [0:31] | Intrinsic I/O delay + 1×Minimum + input_val × Chain Delay | TBD | TBD | TBD | ps |
2 (INVALID) | — | — | — | — | — | — |
3 | [0:31] | Intrinsic I/O delay + 2×Minimum + input_val × Chain Delay | TBD | TBD | TBD | ps |
You can program the number of delay steps by adjusting the I/O Delay register (io0_delay through io47_delay for I/Os 0 through 47).
Configuration Specifications
General Configuration Timing Specifications
Symbol | Description | Requirement | Unit | ||
---|---|---|---|---|---|
Min | Max | ||||
tCF12ST1 68 | nCONFIG high to nSTATUS high | — | 20 | ms | |
tCF02ST0 | nCONFIG low to nSTATUS low | — | 400 | ms | |
tST0 | nSTATUS low pulse during configuration error | 0.5 | 1.5 | ms | |
tCD2UM 69 | CONF_DONE high to user mode | — | 2 | ms |
POR Specifications
Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration.
POR Delay | Minimum | Maximum | Unit |
---|---|---|---|
AS (Normal mode), AVST ×8, AVST ×16, AVST ×32, SD/MMC | 11 | 17 | ms |
AS (Fast mode) | 1.1 | 6.9 | ms |
External Configuration Clock Source Requirements
Description | External Clock Source | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Clock input frequency 70 | Powered by VCCIO_SDM | 25/100/125 | MHz | ||
Clock input jitter tolerance | — | — | 2 | % | |
Clock input duty cycle | 45 | 50 | 55 | % |
JTAG Configuration Timing
Symbol | Description | Requirement | Unit | |
---|---|---|---|---|
Minimum | Maximum | |||
tJCP | TCK clock period | 30 | — | ns |
tJCH | TCK clock high time | 14 | — | ns |
tJCL | TCK clock low time | 14 | — | ns |
tJPSU (TDI) | TDI JTAG port setup time | 2 | — | ns |
tJPSU (TMS) | TMS JTAG port setup time | 3 | — | ns |
tJPH | JTAG port hold time | 5 | — | ns |
tJPCO | JTAG port clock to output | — | 7 | ns |
tJPZX | JTAG port high impedance to valid output | — | 14 | ns |
tJPXZ | JTAG port valid output to high impedance | — | 14 | ns |
AS Configuration Timing
Symbol | Description | Minimum | Typical | Maximum | Unit | |
---|---|---|---|---|---|---|
Tclk | AS_CLK clock period | — | 7.52 | — | ns | |
Tdutycycle | AS_CLK duty cycle | 45 | 50 | 55 | % | |
Tdcsfrs | AS_nCSO[3:0] asserted to first AS_CLK edge | 4.21 71 | — | 7.50 71 | ns | |
Tdcslst | Last AS_CLK edge to AS_nCSO[3:0] deasserted | 5.18 71 | — | 8 71 | ns | |
Tdo | AS_DATA0 output delay | 0 | — | 1.572 | ns | |
Text_delay 73 | Total external propagation delay on AS signals | 0 | — | 15 | ns | |
Tdcsb2b | Minimum delay of slave select deassertion between two back-to-back transfers | 1 | — | — | AS_CLK |
Text_delay = Tbd_clk + Tco + Tbd_data + Tadd
Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.
Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the minimum and maximum specification values.
Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.
Tadd: Propagation delay for active/passive components on AS_DATA interfaces.
Avalon-ST Configuration Timing
Symbol | Description | Minimum | Unit |
---|---|---|---|
tACLKH | AVST_CLK high time | 3.6 | ns |
tACLKL | AVST_CLK low time | 3.6 | ns |
tACLKP | AVST_CLK period | 8 | ns |
tADSU 74 | AVST_DATA setup time before rising edge of AVST_CLK | 5.5 | ns |
tADH 74 | AVST_DATA hold time after rising edge of AVST_CLK | 0 | ns |
tAVSU | AVST_VALID setup time before rising edge of AVST_CLK | 5.5 | ns |
tAVDH | AVST_VALID hold time after rising edge of AVST_CLK | 0 | ns |
I/O Timing
I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing analysis. You may generate the I/O timing report manually using the Timing Analyzer.
The Intel® Quartus® Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route.
Glossary
Term | Definition |
---|---|
Differential I/O Standards | Receiver Input
Waveforms
Transmitter Output Waveforms
|
fHSCLK | I/O PLL input clock frequency. |
fHSDR | LVDS SERDES block—maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. |
fHSDRDPA | LVDS SERDES block—maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. |
J (SERDES factor) | LVDS SERDES block—deserialization factor (width of parallel data bus). |
JTAG Timing Specifications | JTAG Timing
Specifications:
|
RL | Receiver differential input discrete resistor (external to the Intel® Agilex™ device). |
Sampling window (SW) | Timing Diagram—the
period of time during which the data must be valid in order to capture it
correctly. The setup and hold times determine the ideal strobe position in the
sampling window, as shown:
|
Single-ended voltage referenced I/O standard | The JEDEC standard
for the SSTL and HSTL I/O defines both the AC and DC input signal values. The
AC values indicate the voltage levels at which the receiver must meet its
timing specifications. The DC values indicate the voltage levels at which the
final logic state of the receiver is unambiguously defined. After the receiver
input has crossed the AC value, the receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Single-Ended Voltage Referenced I/O Standard
|
tC | High-speed receiver/transmitter input and output clock period. |
TCCS (channel-to-channel-skew) | The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). |
tDUTY | LVDS SERDES block—duty cycle on high-speed transmitter output clock. |
tFALL | Signal high-to-low transition time (80–20%). |
tINCCJ | Cycle-to-cycle jitter tolerance on the PLL clock input. |
tOUTPJ_IO | Period jitter on the GPIO driven by a PLL. |
tOUTPJ_DC | Period jitter on the dedicated clock output driven by a PLL. |
tRISE | Signal low-to-high transition time (20–80%). |
Timing Unit Interval (TUI) | The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w). |
VCM(DC) | DC Common mode input voltage. |
VICM | Input Common mode voltage—the common mode of the differential signal at the receiver. |
VICM(DC) | VCM(DC) DC Common mode input voltage. |
VID | Input differential voltage swing—the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. |
VDIF(AC) | AC differential input voltage—minimum AC input differential voltage required for switching. |
VDIF(DC) | DC differential input voltage—minimum DC input differential voltage required for switching. |
VIH | Voltage input high—the minimum positive voltage applied to the input which is accepted by the device as a logic high. |
VIH(AC) | High-level AC input voltage. |
VIH(DC) | High-level DC input voltage. |
VIL | Voltage input low—the maximum positive voltage applied to the input which is accepted by the device as a logic low. |
VIL(AC) | Low-level AC input voltage. |
VIL(DC) | Low-level DC input voltage. |
VOCM | Output Common mode voltage—the common mode of the differential signal at the transmitter. |
VOD | Output differential voltage swing—the difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter. |
VSWING | Differential input voltage. |
VOX | Output differential cross point voltage. |
VIX(AC) | VIX Input differential cross point voltage. |
W | LVDS SERDES block—Clock Boost Factor. |
Document Revision History for the Intel Agilex Device Data Sheet
Document Version | Changes |
---|---|
2019.04.02 | Initial release. |