Intel Agilex Device Data Sheet

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DS-1060 | 2021.06.02

Intel Agilex Device Data Sheet

This data sheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel^® Agilex™ devices.

Until the data sheet status for a device reaches Final, the specifications are subject to change at any time and at Intel^®'s discretion.

Table 1. Data Sheet Status for Intel^® Agilex™ Devices (F-Series)
Device	Tile	Package	Status
AGF 012/014	E-Tile & P-Tile	R24A	Preliminary
AGF 022/027	E-Tile & P-Tile	R25A	Preliminary
AGF 006/008	F-Tile	R16A	Advance
AGF 006/008/012/014/022/027	F-Tile	R24C	Advance
AGF 022/027	F-Tile	R31C	Advance

Table 2. Data Sheet Status for Intel^® Agilex™ Devices (I-Series)
Device	Tile	Package	Status
AGI 022/027	R-Tile & F-Tile	R29A	Advance
AGI 022/027	R-Tile & F-Tile	R31A	Advance
AGI 022/027	F-Tile	R31B	Advance

The following descriptors designate the status level currently applicable to the relevant variant:

Advance: These are target specifications based on simulation.
Preliminary: These specifications are based on simulation, early validation, and/or early characterization data.
Final: These are production specifications based on silicon validation and/or characterization.

Table 3. Intel^® Agilex™ Device Grades, Core Speed Grades, and Power Options Supported For specification status, see the Data Sheet Status table
Device Grade	Speed Grade and Power Option Supported
Extended	–E1V (fastest)
	–E2V
	–E3V
	–E3E
	–E4X
	–E4F
Industrial	–I1V
	–I2V
	–I3V
	–I3E

The suffix after the speed grade denotes the power options offered in Intel^® Agilex™ devices.

V—standard power (VID)
E—lower power (VID)
X—lowest power (VID)
F—fixed voltage

Electrical Characteristics

The following sections describe the operating conditions and power consumption of Intel^® Agilex™ devices.

Operating Conditions

Intel^® Agilex™ devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel^® Agilex™ devices, you must consider the operating requirements described in this section.

Absolute Maximum Ratings

This section defines the maximum operating conditions for Intel^® Agilex™ devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.

CAUTION:

Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.

Table 4. Absolute Maximum Rating for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Condition	Minimum	Maximum	Unit
V_CC	Core voltage power supply	—	–0.5	1.14	V
V_CCP	Periphery circuitry power supply	—	–0.5	1.14	V
V_CCPT	Power supply for I/O PLL and I/O pre-driver	—	–0.5	2.08	V
V_{CCR_CORE}	CRAM power supply	—	–0.5	1.64	V
V_CCH	Transceiver digital power supply	E-tile and P-tile devices	–0.5	1.21	V
V_{CCH_SDM}	SDM block transceiver digital power sense	E-tile and P-tile devices	–0.5	1.21	V
V_{CCIO_PIO_SDM}	SDM block I/O bank power sense of bank 3A	—	–0.5	2.01	V
V_{CCIO_SDM}	SDM block configuration pins power supply	—	–0.5	2.08	V
V_{CCL_SDM}	SDM block core voltage power supply	—	–0.5	1.07	V
V_{CCFUSEWR_SDM}	SDM block fuse writing power supply	—	–0.5	2.4	V
V_{CCPLLDIG_SDM}	SDM block PLL digital power supply	—	–0.5	1.07	V
V_{CCPLL_SDM}	SDM block PLL analog power supply	—	–0.5	2.08	V
V_CCBAT	Battery back-up power supply (For design security volatile key register)	—	–0.5	2.08	V
V_CCADC	ADC voltage sensor power supply	—	–0.5	2.08	V
V_{CCIO_PIO}	I/O bank power supply	—	–0.5	2.01	V
V_{CCA_PLL}	I/O clock network power supply	—	–0.5	1.64	V
V_{CCRT_GXE}	Transceiver power supply	E-tile devices	–0.5	1.21	V
V_{CC_HSSI_GXE}	E-tile digital signal power supply	E-tile devices	–0.5	1.21	V
V_{CCRTPLL_GXE}	Transceiver PLL power supply	E-tile devices	–0.5	1.21	V
V_{CCH_GXE}	Analog power supply	E-tile devices	–0.5	1.47	V
V_{CCCLK_GXE}	LVPECL `REFCLK` power supply	E-tile devices	–0.5	3.41	V
V_{CCRT_GXP}	Transceiver power supply	P-tile devices	–0.5	1.21	V
V_{CC_HSSI_GXP}	P-tile digital signal power supply	P-tile devices	–0.5	1.21	V
V_{CCFUSE_GXP}	P-tile efuse power supply	P-tile devices	–0.5	1.21	V
V_{CCCLK_GXP}	P-tile I/O buffer power supply	P-tile devices	–0.5	2.46	V
V_{CCH_GXP}	High voltage power for transceiver	P-tile devices	–0.5	2.46	V
V_{CCEHT_GXR}	Transceiver analog high voltage power	R-tile devices	1.75	1.85	V
V_{CCERT_GXR}	Transceiver analog power supply	R-tile devices	0.97	1.03	V
V_{CCED_GXR}	Transceiver digital power supply	R-tile devices	0.87	0.93	V
V_{CCE_PLL_GXR}	PLLs power supply	R-tile devices	0.98	1.02	V
V_{CCE_DTS_GXR}	DTS power supply	R-tile devices	0.98	1.02	V
V_{CCCLK_GXR}	Reference clock power supply	R-tile devices	0.97	1.03	V
V_{CCHFUSE_GXR}	R-tile efuse power supply	R-tile devices	0.97	1.03	V
V_{CC_HSSI_GXR}	Digital signal power supply	R-tile devices	0.87	0.93	V
V_{CCERT1_FHT_GXF}	FHT analog core supply 1	F-tile devices	0.975	1.33	V
V_{CCERT2_FHT_GXF}	FHT analog core supply 2	F-tile devices	0.975	1.33	V
V_{CCEHT_FHT_GXF}	FHT high voltage power supply for analog circuit	F-tile devices	1.47	1.99	V
V_{CCERT_FGT_GXF}	FGT analog core supply	F-tile devices	0.97	1.34	V
V_{CCEH_FGT_GXF}	FGT analog I/O power supply	F-tile devices	1.746	2.41	V
V_{CCERT_GXF_COMBINE}	Combined analog core supply	F-tile devices	0.975	1.33	V
V_{CCL_HPS}	HPS core voltage and periphery circuitry power supply	—	–0.5	1.21	V
V_{CCPLLDIG_HPS}	HPS PLL digital power supply	—	–0.5	1.21	V
V_{CCPLL_HPS}	HPS PLL analog power supply	—	–0.5	2.08	V
V_{CCIO_HPS}	HPS I/O buffers power supply	—	–0.5	2.08	V
V_I	DC input voltage	V_{CCIO_PIO} = 1.2 V	–0.3	1.56	V
		V_{CCIO_PIO} = 1.5 V	0	1.7	V
		V_{CCIO_SDM}, V_{CCIO_HPS} = 1.8 V	–0.3	2.19	V
I_OUT ¹ ²	DC output current per pin	V_{CCIO_PIO} = 1.2 V, 1.5 V ³	–15	15	mA
I_OUT ¹ ²	DC output current per pin	V_{CCIO_SDM}, V_{CCIO_HPS} = 1.8 V ⁴	–20	20	mA
T_J	Absolute junction temperature	—	–55	125	°C
T_STG	Storage temperature	—	–55	150	°C

¹ Total current per I/O bank must not exceed 100 mA.

² Applies to all I/O standards and settings supported by I/O banks, including single-ended and differential I/Os.

³ The maximum current allowed through any I/O bank pin when the device is not turned on or during power-up/power-down conditions is 10 mA. The voltage level must not exceed 1.2 V.

⁴ The maximum current allowed through any HPS/SDM pin when the device is not turned on or during power-up/power-down conditions is 40 mA. The voltage level must not exceed 1.89 V.

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, input signals may overshoot to the voltage listed in the following tables and undershoot to –1.1 V when using V_{CCIO_HPS}/ V_{CCIO_SDM} of 1.8 V and –0.3 V when using V_{CCIO_PIO} of 1.2 V for input currents less than 100 mA and periods shorter than 20 ns.

No overshooting beyond 1.7 V and undershooting below 0 V is allowed when using V_{CCIO_PIO} = 1.5 V.

The maximum allowed overshoot duration is specified as a percentage of high time (calculated as ([delta T]/T) × 100) over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

Table 5. Maximum Allowed Overshoot During Transitions for Intel^® Agilex™ Devices (for 1.2 V I/O in GPIO Bank)
This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table
Symbol	Description	Condition (V)	Overshoot Duration as % at T_J = 100°C	Unit
V_i (AC)	AC input voltage	V_{CCIO_PIO} + 0.30	100	%
		V_{CCIO_PIO} + 0.35	37	%
		V_{CCIO_PIO} + 0.40	9	%
		V_{CCIO_PIO} + 0.45	3	%
		V_{CCIO_PIO} + 0.50	1	%
		> V_{CCIO_PIO} + 0.50	No overshoot allowed	%

Table 6. Maximum Allowed Overshoot During Transitions for Intel^® Agilex™ Devices (for 1.8 V I/O in HPS and SDM I/O Banks)
This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table
Symbol	Description	Condition (V)	Overshoot Duration as % at T_J = 100°C	Unit
V_i (AC)	AC input voltage	V_{CCIO_SDM} + 0.30, V_{CCIO_HPS} + 0.30	100	%
		V_{CCIO_SDM} + 0.35, V_{CCIO_HPS} + 0.35	60	%
		V_{CCIO_SDM} + 0.40, V_{CCIO_HPS} + 0.40	30	%
		V_{CCIO_SDM} + 0.45, V_{CCIO_HPS} + 0.45	20	%
		V_{CCIO_SDM} + 0.50, V_{CCIO_HPS} + 0.50	10	%
		V_{CCIO_SDM} + 0.55, V_{CCIO_HPS} + 0.55	6	%
		>V_{CCIO_SDM} + 0.55, >V_{CCIO_HPS} + 0.55	No overshoot allowed	%

For example, when using 1.2 V I/O standard with 1.26 V V_{CCIO_PIO}, a signal that overshoots to 1.71 V can only be at 1.71 V for ~3% over the lifetime of the device. For an overshoot of 1.56 V, the percentage of high time for the overshoot can be as high as 100% over the lifetime of the device.

Figure 1. Intel^® Agilex™ Devices Overshoot Duration Example (for 1.2 V GPIO Bank at V_{CCIO_PIO} = 1.26 V)

Recommended Operating Conditions

This section lists the functional operation limits for the AC and DC parameters for Intel^® Agilex™ devices.

Recommended Operating Conditions

Table 7. Recommended Operating Conditions for Intel^® Agilex™ Devices
This table lists the steady-state voltage values expected for Intel^® Agilex™ devices. Power supply ramps must all be strictly monotonic, without plateaus.

For specification status, see the Data Sheet Status table
Symbol	Description	Condition	Minimum⁵	Typical	Maximum⁵	Unit
V_CC	Core voltage power supply	SmartVID⁶ : –1V, –2V, –3V, –3E, –4X	(Typical) – 3%	0.70 – 0.90⁷	(Typical) + 3%	V
V_CC	Core voltage power supply	Fixed voltage: –4F	0.776	0.8	0.824	V
V_CCP	Periphery circuitry power supply	SmartVID⁶: –1V, –2V, –3V, –3E, –4X	(Typical) – 3%	0.70 – 0.90⁷	(Typical) + 3%	V
V_CCP	Periphery circuitry power supply	Fixed voltage: –4F	0.776	0.8	0.824	V
V_CCPT	Power supply for I/O PLL and I/O pre-driver	—	1.71	1.8	1.89	V
V_{CCR_CORE}	CRAM power supply	—	1.14	1.2	1.26	V
V_CCH	Advanced interface bus (AIB) power supply	E-tile and P-tile devices	0.87	0.9	0.93	V
V_CCH	Advanced interface bus (AIB) power supply	R-tile and F-tile devices	0.776	0.8	0.824	V
V_{CCH_SDM}	SDM block transceiver digital power sense	—	0.87	0.9	0.93	V
V_{CCIO_PIO_SDM} ⁸	SDM block I/O bank power sense of Bank 3A	1.5 V	1.455	1.5	1.545	V
V_{CCIO_PIO_SDM} ⁸	SDM block I/O bank power sense of Bank 3A	1.2 V	1.14	1.2	1.26	V
V_{CCIO_SDM}	SDM block configuration pins power supply	—	1.71	1.8	1.89	V
V_{CCL_SDM}	SDM block core voltage power supply	—	0.776	0.8	0.824	V
V_{CCFUSEWR_SDM}	SDM block fuse writing power supply	—	1.75	1.8	1.85	V
V_{CCPLLDIG_SDM}	SDM block PLL digital power supply	—	0.776	0.8	0.824	V
V_{CCPLL_SDM}	SDM block PLL analog power supply	—	1.71	1.8	1.89	V
V_CCBAT ⁹	Battery back-up power supply (For design security volatile key register)	—	1	—	1.8	V
V_CCADC	ADC voltage sensor power supply	—	1.71	1.8	1.89	V
V_{CCIO_PIO}	I/O bank power supply	1.5 V	1.455	1.5	1.545	V
V_{CCIO_PIO}	I/O bank power supply	1.2 V	1.14	1.2	1.26	V
V_{CCA_PLL}	I/O clock network power supply	—	1.14	1.2	1.26	V
V_I ¹⁰	DC input voltage	V_{CCIO_PIO} = 1.2 V	–0.3	—	V_{CCIO_PIO} + 0.3	V
		V_{CCIO_PIO} = 1.5 V	0	—	1.7	V
		V_{CCIO_SDM}, V_{CCIO_HPS} = 1.8 V	–0.3	—	V_{CCIO_SDM} + 0.3, V_{CCIO_HPS} + 0.3	V
V_O	Output voltage	—	0	—	V_{CCIO_PIO}	V
T_J	Operating junction temperature	Extended	0	—	100	°C
T_J	Operating junction temperature	Industrial	–40¹¹	—	100	°C
t_RAMP ¹² ¹³	Power supply ramp time	Standard POR	200 μs	—	100 ms	—

⁵ This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise.

⁶ The use of Power Management Bus (PMBus*) voltage regulator dedicated to Intel^® Agilex™ SmartVID devices is mandatory. The PMBus* voltage regulator and Intel^® Agilex™ SmartVID devices are connected via PMBus*.

⁷ The typical value is based on the SmartVID programmed value.

⁸ Must be powered up with the same voltage level as V_{CCIO_PIO_3A}. Must be supplied at 1.2 V when using Avalon^®-ST ×16/×32 configuration schemes.

⁹ You need to always power up V_CCBAT. If you do not use the design security feature in Intel^® Agilex™ devices, connect V_CCBAT to a 1.8 V power supply.

¹⁰ This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.

¹¹ E-tile supports an operating temperature range of –40°C to 100°C. However, the E-tile transceivers may experience a higher error rate from –40°C to –20°C because of the calibration procedure when starting at a low temperature. Therefore, the recommended operating temperature range for E-tile protocol-compliant transceiver links is –20°C to 100°C. The maximum temperature ramp rate is 2°C per minute.

¹² t_RAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies.

¹³ To support AS fast mode, all power supplies to the Intel^® Agilex™ device must be fully ramped-up within 10 ms to the recommended operating conditions.

Transceiver Power Supply Operating Conditions

Table 8. E-Tile Transceiver Power Supply Operating Conditions for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Typical DC Level (V)	Recommended DC Setpoint (% of V_nominal)	Recommended VR Ripple (% of V_nominal)	Recommended AC Transient (% of V_nominal)	Maximum (DC Setpoint + Ripple + AC Transient) (% of V_nominal)	Unit
V_{CCRT_GXE} ¹⁴	Transceiver power supply	0.9	± 0.5%	± 2.5%		± 3%	V
V_{CC_HSSI_GXE}	E-tile digital signal power supply	0.9	± 0.5%	± 2.5%		± 3%	V
V_{CCRTPLL_GXE} ¹⁴	Transceiver PLL power supply	0.9	± 0.5%	± 2.5%		± 3%	V
V_{CCH_GXE}	Analog power supply	1.1	± 0.5%	± 0.5%	± 2%	± 3%	V
V_{CCCLK_GXE}	LVPECL REFCLK power supply	2.5	± 0.5%	± 0.5%	± 3.5%	± 5%	V

Table 9. P-Tile Transceiver Power Supply Operating Conditions for Intel^® Agilex™ Devices
The specifications below should be met at the board vias directly connected to the package power balls. Place the VR sense point in the FPGA pinfield (in the package shadow), as close as possible to the corresponding package power balls. For these rails, measure the output voltage at this remote sense location.

For specification status, see the Data Sheet Status table
Symbol	Description	Typical DC Level (V)	Recommended DC Setpoint (% of V_nominal)	Recommended VR Ripple (% of V_nominal)	Recommended AC Transient (% of V_nominal)	Maximum (DC Setpoint + Ripple + AC Transient) (% of V_nominal)	Unit
V_{CCRT_GXP}	Transceiver power supply	0.9	± 0.5%	± 2.5%		± 3%	V
V_{CC_HSSI_GXP}	P-tile digital signal power supply	0.9	± 0.5%	± 2.5%		± 3%	V
V_{CCFUSE_GXP}	P-tile efuse power supply	0.9	± 0.5%	± 2.5%		± 3%	V
V_{CCCLK_GXP}	P-tile I/O buffer power supply	1.8	± 0.5%	± 0.5%	± 2%	± 3%	V
V_{CCH_GXP}	High voltage power for transceiver	1.8	± 0.5%	± 0.5%	± 2%	± 3%	V

Table 10. R-Tile Transceiver Power Supply Operating Conditions for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Typical DC Level (V)	Recommended DC Setpoint (% of Vnominal)	Recommended VR Ripple (% of Vnominal)	Maximum (DC Setpoint + Ripple + AC Transient) (% of Vnominal)	Unit
V_{CCEHT_GXR[L,R]}	Transceiver analog high voltage power	1.8	±0.5%	±2%	±2.5%	V
V_{CCERT_GXR[L,R]}	Transceiver analog power supply	1	±0.5%	±2.5%	±3%	V
V_{CCED_GXR[L,R]}	Transceiver digital power supply	0.9	±0.5%	±2.5%	±3%	V
V_{CCE_PLL_GXR[L,R]}	PLLs power supply	1	±0.5%	±1.5%	±2%	V
V_{CCE_DTS_GXR[L,R]}	DTS power supply	1	±0.5%	±1.5%	±2%	V
V_{CCCLK_GXR[L,R]}	Reference clock power supply	1	±0.5%	±1.5%	±2%	V
V_{CCHFUSE_GXR}	R-tile efuse power supply	1	±0.5%	±2.5%	±3%	V
V_{CC_HSSI_GXR}	Digital signal power supply	0.9	±0.5%	±2.5%	±3%	V

Table 11. F-Tile Transceiver Power Supply Operating Conditions for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Typical DC Level (V)	Recommended DC Setpoint (% of Vnominal)	Recommended VR Ripple (% of Vnominal)	Recommended AC Transient (% of Vnominal)	Maximum (DC Setpoint + Ripple + AC Transient) (% of Vnominal)	Unit
V_{CC_HSSI_GXF}	F-tile digital signal power supply	0.8	±0.5%	±0.5%	±2.5%	±3%	V
V_{CCFUSECORE_GXF}	F-tile fuse writing power supply	1	±0.5%	±4.5%		±5%	V
V_{CCFUSEWR_GXF}	F-tile efuse power supply	1	±0.5%	±4.5%		±5%	V
V_{CCCLK_GXF}	Reference clock power supply	1.8	±0.5%	±0.5%	±2%	±3%	V
V_{CCERT1_FHT_GXF} ¹⁵	FHT analog core supply 1	1	±0.5%	±0.5%	±1.5%	±2.5%	V
V_{CCERT2_FHT_GXF} ¹⁶	FHT analog core supply 2	1	±0.5%	±0.5%	±1.5%	±2.5%	V
V_{CCEHT_FHT_GXF} ¹⁷	FHT high voltage power supply for analog circuit	1.5	±0.5%	±0.5%	+1%/–1.5%	+2%/–2.5%	V
V_{CCERT_FGT_GXF} ¹⁸	FGT analog core supply alone	1	±0.5%	±0.5%	±1.5%	±3%	V
V_{CCERT_FGT_GXF} ¹⁸	FGT analog core supply when combined with V_{CCERT1_FHT_GX} and V_{CCERT2_FHT_GXF} 1 V supply	1	±0.5%	±0.5%	±1.5%	±2.5%	V
V_{CCH_FGT_GXF} ¹⁸	FGT analog I/O power supply	1.8	±0.5%	≤5 mV	±1.5%	±3%	V

¹⁴ The difference between V_CCRT/V_CCRTPLL and V_CCH should be no less than 200 mV.

¹⁵ HF noise requires AC 10 mVpp above 1 MHz; switching regulator ripple switching frequency: <500 kHz, ripple: ≤5 mVpp.

¹⁶ HF noise requires AC 30 mVpp above 1 MHz; switching regulator ripple switching frequency: <500 kHz, ripple: ≤5 mVpp.

¹⁷ HF noise requires AC 30 mVpp above 1 MHz; switching regulator ripple switching frequency: <500 kHz, ripple: ≤7 mVpp.

¹⁸ HF noise requires AC 30 mVpp above 1 MHz; switching regulator ripple: ≤5mVpp.

HPS Power Supply Operating Conditions

Table 12. HPS Power Supply Operating Conditions for Intel^® Agilex™ Devices
This table lists the steady-state voltage and current values expected for Intel^® Agilex™ system-on-a-chip (SoC) devices with ARM-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions for Intel^® Agilex™ Devices table for the steady-state voltage values expected from the FPGA portion of the Intel^® Agilex™ SoC devices.

For specification status, see the Data Sheet Status table
Symbol	Description	Condition	Minimum	Typical	Maximum	Unit
V_{CCL_HPS}	HPS core voltage and periphery circuitry power supply	Performance boost, fixed voltage: –1V	(Typical) – 3%	0.95	(Typical) + 3%	V
		SmartVID: –1V, –2V, –3V, –3E ¹⁹	(Typical) – 3%	0.70 – 0.90	(Typical) + 3%	V
		Fixed voltage: –4F, –4X	0.776	0.8	0.824	V
V_{CCPLLDIG_HPS}	HPS PLL digital power supply (can be connected to V_{CCL_HPS})	Performance boost, fixed voltage: –1V	(Typical) – 3%	0.95	(Typical) + 3%	V
		SmartVID: –1V, –2V, –3V, –3E ¹⁹	(Typical) – 3%	0.70 – 0.90	(Typical) + 3%	V
		Fixed voltage: –4F, –4X	0.776	0.8	0.824	V
V_{CCPLL_HPS}	HPS PLL analog power supply	1.8 V	1.71	1.8	1.89	V
V_{CCIO_HPS}	HPS I/O buffers power supply	1.8 V	1.71	1.8	1.89	V

¹⁹ The use of Power Management Bus (PMBus*) voltage regulator dedicated to Intel^® Agilex™ SmartVID devices is mandatory. The PMBus* voltage regulator and Intel^® Agilex™ SmartVID devices are connected via PMBus*.

DC Characteristics

Supply Current and Power Consumption

Intel^® offers two ways to estimate power for your design—the Intel^® FPGA Power and Thermal Calculator (PTC) and the Intel^® Quartus^® Prime Power Analyzer feature.

Use the PTC before you start your design to estimate the supply current for your design. The PTC provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources.

The Intel^® Quartus^® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates.

I/O Pin Leakage Current

Table 13. I/O Pin Leakage Current for Intel^® Agilex™ Devices (for GPIO Bank) For specification status, see the Data Sheet Status table
Symbol	Description	Condition	Min	Max	Unit
I_I	Input pin	V_I = 0 V to V_{CCIO_PIO (MAX)}	–360	360	µA
I_OZ	Tri-stated I/O pin	V_O = 0 V to V_{CCIO_PIO (MAX)}	–360	360	µA

Table 14. I/O Pin Leakage Current for Intel^® Agilex™ Devices (for HPS and SDM I/O Banks) For specification status, see the Data Sheet Status table
Symbol	Description	Condition	Min	Max	Unit
I_I	Input or tri-stated I/O pin	V_I, V_O = 0 V	0.015	6	µA
I_I	Input or tri-stated I/O pin	V_I, V_O = V_{CCIO_HPS (MAX)}, V_{CCIO_SDM (MAX)}	0.01	1	µA

Bus Hold Specifications

The bus-hold trip points are based on calculated input voltages from the JEDEC* standard.

Table 15. Bus Hold Parameters for Intel^® Agilex™ Devices (for GPIO Bank) For specification status, see the Data Sheet Status table
Parameter	Symbol	Condition	V_{CCIO_PIO} (V)		Unit
			1.2
			Min	Max
Bus-hold, low, sustaining current	I_SUSL	V_IN > V_IL (max)	50	—	µA
Bus-hold, high, sustaining current	I_SUSH	V_IN < V_IH (min)	–50	—	µA
Bus-hold, low, overdrive current	I_ODL	0 V < V_IN < V_{CCIO_PIO}	—	1,400	µA
Bus-hold, high, overdrive current	I_ODH	0 V < V_IN < V_{CCIO_PIO}	—	–1,400	µA
Bus-hold trip point	V_TRIP	—	0.33 × V_{CCIO_PIO}	0.67 × V_{CCIO_PIO}	V

OCT Calibration Accuracy Specifications

If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block.

Table 16. OCT Calibration Accuracy Specifications for Intel^® Agilex™ Devices (for GPIO Bank)
Calibration accuracy for the calibrated on-chip series termination (R_S OCT) and on-chip parallel termination (R_T OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.

These specifications require RZQ reference accuracy of 240 Ω ±1%.

For specification status, see the Data Sheet Status table
Symbol	Description	Condition (V)	Calibration Accuracy	Unit
34-Ω and 40-Ω R_S	Internal series termination with calibration (34-Ω and 40-Ω setting)	V_{CCIO_PIO} = 1.2	±20	%
50-Ω and 60-Ω R_T	Internal parallel termination with calibration (50-Ω and 60-Ω setting)	SSTL-12 and HSTL-12 I/O standards	–10 to +60	%
50-Ω and 60-Ω R_T		POD12 I/O standard	±15	%

OCT Without Calibration Resistance Tolerance Specifications

Table 17. OCT Without Calibration Resistance Tolerance Specifications for Intel^® Agilex™ Devices (for GPIO Bank)
This table lists the Intel^® Agilex™ GPIO OCT without calibration resistance tolerance to PVT changes.

For specification status, see the Data Sheet Status table
Symbol	Description	Condition (V)	Calibration Accuracy	Unit
34-Ω and 40-Ω R_S	Internal series termination without calibration (34-Ω and 40-Ω setting)	V_{CCIO_PIO} = 1.2	–30 to +60	%
100-Ω R_D	Internal differential termination (100-Ω setting)	V_{CCIO_PIO} = 1.5	±40	%
100-Ω R_D	Internal differential termination (100-Ω setting)	V_{CCIO_PIO} = 1.2	±40	%

Pin Capacitance

Table 18. Pin Capacitance for Intel^® Agilex™ Devices (for GPIO Bank) For specification status, see the Data Sheet Status table
Symbol	Description	Maximum	Unit
C_IO	Input/output capacitance of I/O pins	2.6²⁰	pF

²⁰ This value refers to die-level pin capacitance without the device package.

Internal Weak Pull-Up Resistor

All I/O pins, except configuration and JTAG pins, have an option to enable weak pull-up. For SDM and HPS, the configuration I/O and peripheral I/O are supported with weak pull-up and weak pull-down options.

Table 19. Internal Weak Pull-Up Resistor Values for Intel^® Agilex™ Devices (for GPIO Bank) For specification status, see the Data Sheet Status table
Symbol	Description	Condition (V)	Min	Typ	Max	Unit
R_PU	Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option.	V_{CCIO_PIO} = 1.2 ±5%	0.5	2.5	15	kΩ

Table 20. Internal Weak Pull-Up and Weak Pull-Down Resistor Values for Intel^® Agilex™ Devices (for HPS and SDM I/O Banks) For specification status, see the Data Sheet Status table
Symbol	Description	Condition (V)	Min	Typ	Max	Unit
20 kΩ R_PU, 20 kΩ R_PD	Value of the I/O pin pull-up and pull-down resistor during user mode if you have enabled the programmable pull-up or pull-down resistor option.	V_{CCIO_SDM} = 1.8 ±5%, V_{CCIO_HPS} = 1.8 ±5%	15	20	25	kΩ
50 kΩ R_PU, 50 kΩ R_PD	Value of the I/O pin pull-up and pull-down resistor during user mode if you have enabled the programmable pull-up or pull-down resistor option.	V_{CCIO_SDM} = 1.8 ±5%, V_{CCIO_HPS} = 1.8 ±5%	37.5	50	62.5	kΩ
80 kΩ R_PU, 80 kΩ R_PD	Value of the I/O pin pull-up and pull-down resistor during user mode if you have enabled the programmable pull-up or pull-down resistor option.	V_{CCIO_SDM} = 1.8 ±5%, V_{CCIO_HPS} = 1.8 ±5%	60	80	100	kΩ

Hysteresis Specifications for Schmitt Trigger Input

Table 21. Hysteresis Specifications for Schmitt Trigger Input for Intel^® Agilex™ Devices (for HPS I/O Bank)
Intel^® Agilex™ devices support Schmitt trigger input on HPS I/O bank. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signal with slow edge rate.

For specification status, see the Data Sheet Status table
Symbol	Description	Condition	Min	Typ	Max	Unit
V_HYS	Hysteresis for Schmitt trigger input	V_{CCIO_HPS} = 1.8 V	180	250	350	mV

I/O Standard Specifications

Tables in this section list the input voltage (V_IH and V_IL), output voltage (V_OH and V_OL), and current drive characteristics (I_OH and I_OL) for various I/O standards supported by Intel^® Agilex™ devices.

For minimum voltage values, use the minimum V_{CCIO_PIO} values. For maximum voltage values, use the maximum V_{CCIO_PIO} values.

You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

Single-Ended I/O Standards Specifications

Table 22. Single-Ended I/O Standards Specifications for Intel^® Agilex™ Devices (for GPIO Bank) For specification status, see the Data Sheet Status table
I/O Standard	V_{CCIO_PIO} (V)			V_IL(V)		V_IH(V)		V_OL(V)²¹	V_OH(V)²¹
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Max	Min
1.2 V LVCMOS	1.14	1.2	1.26	–0.3	0.35 × V_{CCIO_PIO}	0.65 × V_{CCIO_PIO}	V_{CCIO_PIO} + 0.3	0.25 × V_{CCIO_PIO}	0.75 × V_{CCIO_PIO}

Table 23. Single-Ended I/O Standards Specifications for Intel^® Agilex™ Devices (for HPS and SDM I/O Banks) For specification status, see the Data Sheet Status table
I/O Standard	V_{CCIO_HPS}, V_{CCIO_SDM} (V)			V_IL(V)		V_IH(V)		V_OL(V)	V_OH(V)	I_OL (mA)²²	I_OH (mA)²²
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Max	Min	Max	Min
1.8 V LVCMOS	1.71	1.8	1.89	—	0.35 × V_{CCIO_HPS}, 0.35 × V_{CCIO_SDM}	0.65 × V_{CCIO_HPS}, 0.65 × V_{CCIO_SDM}	—	0.4	V_{CCIO_HPS} – 0.4, V_{CCIO_SDM} – 0.4	8	–8

²¹ Applicable to test condition of I_OH and I_OL at 2 mA.

²² To meet the I_OH and I_OL specifications, you must set the current strength settings accordingly. For example, to meet the 1.8 V LVCMOS specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the I_OH and I_OL specifications in the data sheet.

Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications

Table 24. Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications for Intel^® Agilex™ Devices (for GPIO Bank) For specification status, see the Data Sheet Status table
I/O Standard	V_{CCIO_PIO} (V)			V_REF (V)			V_TT (V)
I/O Standard	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max
SSTL-12	1.14	1.2	1.26	0.49 × V_{CCIO_PIO}	0.5 × V_{CCIO_PIO}	0.51 × V_{CCIO_PIO}	0.475 × V_{CCIO_PIO}	0.5 × V_{CCIO_PIO}	0.525 × V_{CCIO_PIO}
HSTL-12	1.14	1.2	1.26	0.47 × V_{CCIO_PIO}	0.5 × V_{CCIO_PIO}	0.53 × V_{CCIO_PIO}	0.475 × V_{CCIO_PIO}	0.5 × V_{CCIO_PIO}	0.525 × V_{CCIO_PIO}
HSUL-12	1.14	1.2	1.26	0.49 × V_{CCIO_PIO}	0.5 × V_{CCIO_PIO}	0.51 × V_{CCIO_PIO}	—	—	—
POD12	1.14	1.2	1.26	—	Internally calibrated	—	—	V_{CCIO_PIO}	—

Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications

Table 25. Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications for Intel^® Agilex™ Devices (for GPIO Bank) For specification status, see the Data Sheet Status table
I/O Standard	V_IL(DC) (V)	V_IH(DC) (V)	V_IL(AC) (V)	V_IH(AC) (V)
I/O Standard	Max	Min	Max	Min
SSTL-12	V_REF – 0.075	V_REF + 0.075	V_REF – 0.100	V_REF + 0.100
HSTL-12	V_REF – 0.080	V_REF + 0.080	V_REF – 0.150	V_REF + 0.150
HSUL-12	V_REF – 0.100	V_REF + 0.100	V_REF – 0.135	V_REF + 0.135
POD12²³	V_REF – 0.055	V_REF + 0.055	V_REF – 0.070	V_REF + 0.070

Note: For output voltage swing calculation example, refer to the Intel^® Agilex™ General Purpose I/O and LVDS SERDES User Guide.

²³ This specification is defined over internal V_ref range from 0.6 × V_{CCIO_PIO} to 0.92 × V_{CCIO_PIO}.

Differential SSTL, HSTL, and HSUL I/O Standards Specifications

Table 26. Differential SSTL, HSTL, and HSUL I/O Standards Specifications for Intel^® Agilex™ Devices (for GPIO Bank) For specification status, see the Data Sheet Status table
I/O Standard	V_{CCIO_PIO} (V)			V_ILdiff(DC) (V)	V_IHdiff(DC) (V)	V_ILdiff(AC) (V)	V_IHdiff(AC) (V)	V_IX(AC) (V)			V_OX(AC) (V)
I/O Standard	Min	Typ	Max	Max	Min	Max	Min	Min	Typ	Max	Min	Typ	Max
SSTL-12	1.14	1.2	1.26	–0.15	0.15	–0.2	0.2	0.5 × V_{CCIO_PIO} – 0.12	0.5 × V_{CCIO_PIO}	0.5 × V_{CCIO_PIO} + 0.12	0.5 × V_{CCIO_PIO} – 0.12	0.5 × V_{CCIO_PIO}	0.5 × V_{CCIO_PIO} + 0.12
HSTL-12	1.14	1.2	1.26	–0.16	0.16	–0.3	0.3	0.5 × V_{CCIO_PIO} – 0.12	0.5 × V_{CCIO_PIO}	0.5 × V_{CCIO_PIO} + 0.12	0.5 × V_{CCIO_PIO} – 0.12	0.5 × V_{CCIO_PIO}	0.5 × V_{CCIO_PIO} + 0.12
HSUL-12	1.14	1.2	1.26	–0.2	0.2	–0.27	0.27	0.5 × V_{CCIO_PIO} – 0.12	0.5 × V_{CCIO_PIO}	0.5 × V_{CCIO_PIO} + 0.12	0.5 × V_{CCIO_PIO} – 0.12	0.5 × V_{CCIO_PIO}	0.5 × V_{CCIO_PIO} + 0.12

Differential POD I/O Standards Specifications

Table 27. Differential POD I/O Standards Specifications for Intel^® Agilex™ Devices (for GPIO Bank) For specification status, see the Data Sheet Status table
I/O Standard	V_{CCIO_PIO} (V)			V_ILdiff(DC) (V)	V_IHdiff(DC) (V)	V_ILdiff(AC) (V)	V_IHdiff(AC) (V)	V_IX(AC) (%)²⁴
I/O Standard	Min	Typ	Max	Max	Min	Max	Min	Max
POD12	1.14	1.2	1.26	–0.11	0.11	–0.14	0.14	25

²⁴ Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings.

Differential I/O Standards Specifications

Table 28. Differential I/O Standards Specifications for Intel^® Agilex™ Devices (for GPIO Bank) For specification status, see the Data Sheet Status table
I/O Standard	V_{CCIO_PIO} (V)			V_ID (mV)		V_ICM(DC) (V)			V_OD (V)²⁵ ²⁶			V_OCM (V)²⁵
I/O Standard	Min	Typ	Max	Min	Max	Min	Condition	Max	Min	Typ	Max	Min	Typ	Max
True Differential Signaling (Transmitter & Receiver)²⁷	1.455	1.5	1.545	200	600	0.3	Data rate ≤700 Mbps	<0.9	0.247	—	0.454	0.99	1.1	1.21
				100	600	0.9	Data rate ≤700 Mbps	1.4
				100	600	0.9	Data rate >700 Mbps	1.4
True Differential Signaling (Receiver only)²⁷	1.14	1.2	1.26	200	600	0.3	Data rate ≤700 Mbps	<0.9	—	—	—	—	—	—
				100	600	0.9	Data rate ≤700 Mbps	1.1
				100	600	0.9	Data rate >700 Mbps	1.1

²⁵ R_L range: 90 ≤ R_L ≤ 110 Ω.

²⁶ The specification is only applicable to default V_OD and pre-emphasis setting.

²⁷ The True Differential Signaling input buffer is supported on 1.2 V and 1.5 V V_{CCIO_PIO} bank. The maximum input voltage driven into the True Differential Signaling input buffer must not exceed V_ICM(max) + V_ID(max)/2.

Switching Characteristics

This section provides the performance characteristics of Intel^® Agilex™ core and periphery blocks.

Core Performance Specifications

Clock Tree Specifications

Table 29. Clock Tree Performance for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Parameter	Performance		Unit
Parameter	–1V, –2V	–3V, –3E, –4F, –4X	Unit
Programmable clock routing	1,000	780	MHz

I/O PLL Specifications

Table 30. I/O PLL Specifications for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Parameter	Condition	Min	Typ	Max	Unit
f_IN	Input clock frequency	–1V	10	—	1,100²⁸	MHz
		–2V	10	—	900²⁸	MHz
		–3V, –3E	10	—	750²⁸	MHz
		–4F, –4X	10	—	650²⁸	MHz
f_INPFD	Input clock frequency to the PFD	—	10	—	325	MHz
f_VCO	I/O PLL VCO operating range	–1V	600	—	1,600	MHz
		–2V	600	—	1,434	MHz
		–3V, –3E	600	—	1,250	MHz
		–4F, –4X	600	—	1,067	MHz
f_CLBW	I/O PLL closed-loop bandwidth	I/O bank I/O PLL	0.5	—	10	MHz
f_CLBW	I/O PLL closed-loop bandwidth	Fabric-feeding I/O PLL	1	—	10	MHz
t_EINDUTY	Input clock or external feedback clock input duty cycle	—	40	—	60	%
f_OUT	Output frequency for internal clock (`C` counter)	–1V	—	—	1,100	MHz
		–2V	—	—	900	MHz
		–3V, –3E	—	—	750	MHz
		–4F, –4X	—	—	650	MHz
f_{OUT_EXT}	Output frequency for external clock output	–1V	—	—	800	MHz
		–2V	—	—	717	MHz
		–3V, –3E	—	—	625	MHz
		–4F, –4X	—	—	500	MHz
t_OUTDUTY	Duty cycle for dedicated external clock output (when set to 50%)	f_{OUT_EXT} < 300 MHz	45	50	55	%
t_OUTDUTY		f_{OUT_EXT} ≥ 300 MHz	40/45 ²⁹	50	55 ²⁹/60	%
t_FCOMP ³⁰	External feedback clock compensation time	—	—	—	5	ns
f_DYCONFIGCLK	Dynamic configuration clock for mgmt_clk	—	—	—	100	MHz
t_LOCK	Time required to lock from end-of-device configuration or deassertion of areset	—	—	—	1	ms
t_DLOCK	Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays)	—	—	—	1	ms
t_{PLL_PSERR}	Accuracy of PLL phase shift	—	—	—	±50	ps
t_ARESET	Minimum pulse width on the areset signal	—	10	—	—	ns
t_INCCJ	Input clock cycle-to-cyle jitter	f_REF < 100 MHz ³¹	—	—	750	ps (p-p)
t_INCCJ	Input clock cycle-to-cyle jitter	f_REF ≥ 100 MHz ³¹	—	—	0.15	UI (p-p)
t_REFPJ	Reference phase jitter (rms)	Carrier frequency: 100 MHz with integrated bandwidth of 10 kHz to 50 MHz	—	—	1.42	ps
t_REFPN	Reference phase noise³²	10 Hz	—	—	–90	dBc/Hz
		100 Hz	—	—	–100	dBc/Hz
		1 kHz	—	—	–110	dBc/Hz
		10 kHz	—	—	–120	dBc/Hz
		100 kHz	—	—	–130	dBc/Hz
		1 MHz	—	—	–138	dBc/Hz
		10 MHz	—	—	–142	dBc/Hz
		100 MHz	—	—	–144	dBc/Hz
t_{OUTPJ_DC} ³⁰ ³³	Period jitter for dedicated clock output	f_OUT < 100 MHz ³¹	—	—	17.5	mUI (p-p)
t_{OUTPJ_DC} ³⁰ ³³	Period jitter for dedicated clock output	f_OUT ≥ 100 MHz ³¹	—	—	175	ps (p-p)
t_{OUTCCJ_DC} ³⁰ ³³	Cycle-to-cycle jitter for dedicated clock output	f_OUT < 100 MHz ³¹	—	—	17.5	mUI (p-p)
t_{OUTCCJ_DC} ³⁰ ³³	Cycle-to-cycle jitter for dedicated clock output	f_OUT ≥ 100 MHz ³¹	—	—	175	ps (p-p)
t_{OUTPJ_IO} ³⁴ ³³	Period jitter for clock output on the regular I/O	f_OUT < 100 MHz ³¹	—	—	60	mUI (p-p)
t_{OUTPJ_IO} ³⁴ ³³	Period jitter for clock output on the regular I/O	f_OUT ≥ 100 MHz ³¹	—	—	600	ps (p-p)
t_{OUTCCJ_IO} ³⁴ ³³	Cycle-to-cycle jitter for clock output on the regular I/O	f_OUT < 100 MHz ³¹	—	—	60	mUI (p-p)
t_{OUTCCJ_IO} ³⁴ ³³	Cycle-to-cycle jitter for clock output on the regular I/O	f_OUT ≥ 100 MHz ³¹	—	—	600	ps (p-p)
t_{CASC_OUTPJ_DC} ³⁰	Period jitter for dedicated clock output in cascaded PLLs	f_OUT < 100 MHz ³¹	—	—	17.5	mUI (p-p)
t_{CASC_OUTPJ_DC} ³⁰	Period jitter for dedicated clock output in cascaded PLLs	f_OUT ≥ 100 MHz ³¹	—	—	175	ps (p-p)

²⁸ This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

²⁹ To achieve 5% duty cycle for f_{OUT_EXT} ≥ 300 MHz, you only can use tx_outclk port from the LVDS SERDES Intel^® FPGA IP. Refer to the Intel^® Agilex™ Clocking and PLL User Guide for the detail design guidelines.

³⁰ Not applicable for fabric-feeding I/O PLL.

³¹ f_REF is f_IN/N, specification applies when N = 1.

³² The phase noise numbers in the table above are the maximum acceptable phase noise values measured at a carrier frequency of 100 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 100 MHz + (20 × log10 (f/100)).

³³ This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend on the spread-spectrum clock profile used. Refer to the Intel^® Agilex™ Clocking and PLL User Guide for the recommended spread-spectrum clock profile.

³⁴ External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory Output Clock Jitter Specifications for Intel^® Agilex™ Devices table.

DSP Block Specifications

Table 31. DSP Block Performance Specifications for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Mode	Performance				Unit
Mode	–1V	–2V	–3V, –3E	–4F, –4X	Unit
Fixed-point 18 × 19 multiplication mode	900	771	676	600	MHz
Fixed-point 27 × 27 multiplication mode³⁵	900	771	676	600	MHz
Fixed-point 18 × 19 multiplier adder mode³⁵	900	771	676	600	MHz
Fixed-point 18 × 19 multiplier adder summed with 36-bit input mode³⁵	900	771	676	600	MHz
Fixed-point four 9 × 9 multiplier adder mode³⁵	900	771	676	600	MHz
Fixed-point 18 × 19 systolic mode	900	771	676	600	MHz
Fixed-point 18 × 19 complex multiplication mode	900	771	676	600	MHz
FP32 floating-point multiplication mode	750	579	507	475	MHz
FP32 floating-point adder or subtract mode	750	579	507	475	MHz
FP32 floating-point multiplier adder or subtract mode	750	579	507	475	MHz
FP32 floating-point multiplier accumulate mode	750	579	507	475	MHz
Addition or subtraction of two FP16 floating-point multiplication mode	750	579	507	475	MHz
Sum/sub of two FP16 multiplications with FP32 (addition/subtraction)	750	579	507	475	MHz
Sum/sub of two FP16 multiplications with accumulation (addition/subtraction)	750	579	507	475	MHz
FP32 floating-point complex multiplication	750	579	507	475	MHz
FP32 floating-point vector dot product	750	579	507	475	MHz
FP16 floating-point complex multiplication	750	579	507	475	MHz
FP16 floating-point vector dot product	750	579	507	475	MHz

³⁵ When Chainout is enabled but systolic registers are not used, the performance specifications for the following speed grades are as follows:

–1V: 675 MHz
–2V: 578 MHz
–3V and –3E: 507 MHz
–4F and –4X: 450 MHz

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel^® Quartus^® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in f_MAX.

Table 32. Memory Block Performance Specifications for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Memory	Mode	Performance				Unit
Memory	Mode	–1V	–2V	–3V, –3E	–4F, –4X	Unit
MLAB	Single-port RAM/ROM Simple dual-port RAM	1,000	782	667	600	MHz
MLAB	Simple dual-port RAM with read-during-write option	630	510	460	330	MHz
M20K Block³⁶	Single-port RAM/ROM Simple dual-port RAM	1,000 (HS) 850 (LP)	782 (HS) 664 (LP)	667 (HS) 567 (LP)	600 (HS) 510 (LP)	MHz
	Simple dual-port RAM, coherent read enabled	1,000 (HS) 850 (LP)	782 (HS) 664 (LP)	667 (HS) 567 (LP)	600 (HS) 510 (LP)	MHz
	Single-port RAM with the read-during-write option set to Old Data Simple dual-port RAM with the read-during-write option set to Old Data	800 (HS) 680 (LP)	640 (HS) 540 (LP)	560 (HS) 476 (LP)	480 (HS) 410 (LP)	MHz
	Simple dual-port RAM with ECC enabled, 512 × 32	600 (HS) 500 (LP)	480 (HS) 400 (LP)	420 (HS) 357 (LP)	360 (HS) 300 (LP)	MHz
	Simple dual-port RAM with ECC, optional pipeline registers enabled, 512 × 32	1,000 (HS) 850 (LP)	782 (HS) 664 (LP)	667 (HS) 567 (LP)	600 (HS) 510 (LP)	MHz
	Dual-port ROM True dual-port RAM	600 (HS)	500 (HS)	420 (HS)	360 (HS)	MHz
	Simple quad-port RAM	600 (HS)	480 (HS)	420 (HS)	360 (HS)	MHz
eSRAM	Simple dual-port	750	640	500	500	MHz

³⁶ For M20K block, timing/power optimization feature is available. The available options are High Speed (HS) and Low Power (LP). For details on this timing/power optimization feature, refer to the Agilex™ Embedded Memory User Guide.

Local Temperature Sensor Specifications

Table 33. Local Temperature Sensor Specifications for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Description	Temperature Range	Accuracy	Sampling Rate³⁷	Conversion Time
Local Temperature Sensor	–40 to 125°C³⁸	±5°C	1 KSPS	< 1 ms

³⁷ The read out is subject to the SDM mailbox activity status.

³⁸ Temperature range refers to junction temperature.

Remote Temperature Diode Specifications

Note the following for the remote temperature diode specifications:

The typical value is at 25°C.
The temperature diode characteristics in this table target for three-currents temperature sensing chip implementation. The characteristics can also apply to two-currents temperature sensing chip implementation.
Absolute accuracy is dependent on third-party external diode ADC and integration specifics.

Table 34. Remote Temperature Diode Specifications for Intel^® Agilex™ Devices (Core Fabric TSD) For specification status, see the Data Sheet Status table
Description	Min	Typ	Max	Unit
I_bias, diode source current	10	—	170	μA
V_bias, voltage across diode	0.43	—	0.75	V
Series resistance	—	—	<3	Ω
Diode ideality factor	—	1.006³⁹	—	—

Table 35. Remote Temperature Diode Specifications for Intel^® Agilex™ Devices (E-Tile TSD) For specification status, see the Data Sheet Status table
Description	Min	Typ	Max	Unit
I_bias, diode source current	10	—	170	μA
V_bias, voltage across diode	0.56	—	0.82	V
Series resistance	—	—	<2	Ω
Diode ideality factor	—	1.005	—	—

Table 36. Remote Temperature Diode Specifications for Intel^® Agilex™ Devices (P-Tile TSD) For specification status, see the Data Sheet Status table
Description	Min	Typ	Max	Unit
I_bias, diode source current	10	—	170	μA
V_bias, voltage across diode	0.56	—	0.87	V
Series resistance	—	—	<10	Ω
Diode ideality factor	—	1.0108⁴⁰	—	—

³⁹ When using lower injection current (two-currents) implementation, the ideality factor is 1.009.

⁴⁰ When using lower injection current (two-currents) implementation, the ideality factor is 1.03.

Voltage Sensor Specifications

Table 37. Voltage Sensor Specifications for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Parameter		Minimum	Typical	Maximum	Unit
Resolution		—	7	—	Bit
Sampling rate⁴¹		—	—	1	KSPS
Input capacitance		—	—	40	pF
Voltage sensor accuracy, V_in range: 0 V to 1.1 V⁴²		—	—	±3.5	%
Unipolar Input Mode	Input signal range for Vsigp	—	—	1.35	V
	Common mode voltage on Vsign	—	—	0.25	V
	Input signal range for Vsigp – Vsign	—	—	1.1	V

⁴¹ The read out is subject to the SDM mailbox activity status.

⁴² For 1.8 V channel 3, 4, 5, and 9, the accuracy is ±4.5%.

Periphery Performance Specifications

This section describes the periphery performance, LVDS SERDES, and external memory interface.

Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

LVDS SERDES Specifications

Table 38. LVDS SERDES Specifications for Intel^® Agilex™ Devices
LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 3 to 10.

DDR registers support SERDES factor J = 1 to 2.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

For specification status, see the Data Sheet Status table
Parameter	Symbol	Condition	–1 Speed Grade			–2 Speed Grade			–3 Speed Grade			–4 Speed Grade			Unit
Parameter	Symbol	Condition	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
Clock frequency	f_{HSCLK_in} (input clock frequency) True Differential I/O Standards	Clock boost factor W = 1 to 40⁴³	10	—	800	10	—	700	10	—	625	10	—	625	MHz
	f_{HSCLK_in} (input clock frequency) Single-Ended I/O Standards	Clock boost factor W = 1 to 40⁴³	10	—	625	10	—	625	10	—	525	10	—	525	MHz
	f_{HSCLK_OUT} (output clock frequency)	—	—	—	800⁴⁴	—	—	700⁴⁴	—	—	625⁴⁴	—	—	625⁴⁴	MHz
Transmitter	True Differential I/O Standards - f_HSDR (data rate)⁴⁵	SERDES factor J = 4 to 10⁴⁶ ⁴⁷ ⁴⁸	150	—	1,600	150	—	1,434	150	—	1,250	150	—	1,000	Mbps
		SERDES factor J = 3⁴⁶ ⁴⁷ ⁴⁸	150	—	1,200	150	—	1,076	150	—	938	150	—	600	Mbps
		SERDES factor J = 2, uses DDR registers	150	—	840⁴⁹	150	—	⁴⁹	150	—	⁴⁹	150	—	⁴⁹	Mbps
		SERDES factor J = 1, uses DDR registers	150	—	420⁴⁹	150	—	⁴⁹	150	—	⁴⁹	150	—	⁴⁹	Mbps
	t_{x Jitter} - True Differential I/O Standards	Total jitter for data rate, 600 Mbps – 1.6 Gbps	≤1,600 Mbps: 160 ≤1,434 Mbps: 200 ≤1,250 Mbps: 250 ≤1,000 Mbps: 300 ≤800 Mbps: 320 600 Mbps: 340			≤1,434 Mbps: 200 ≤1,250 Mbps: 250 ≤1,000 Mbps: 300 ≤800 Mbps: 320 600 Mbps: 340			≤1,250 Mbps: 250 ≤1,000 Mbps: 300 ≤800 Mbps: 320 600 Mbps: 340			≤1,000 Mbps: 300 ≤800 Mbps: 320 600 Mbps: 340			ps
	t_{x Jitter} - True Differential I/O Standards	Total jitter for data rate, < 600 Mbps	—	—	0.21	—	—	0.21	—	—	0.21	—	—	0.21	UI
	t_DUTY ⁵⁰	TX output clock duty cycle for Differential I/O Standards	45	50	55	45	50	55	45	50	55	45	50	55	%
	t_RISE & t_FALL ⁴⁷ ⁵¹	True Differential I/O Standards	—	—	160	—	—	180	—	—	200	—	—	220	ps
	T_CCS ⁴⁵ ⁵⁰	True Differential I/O Standards	—	—	330	—	—	330	—	—	330	—	—	330	ps
Receiver	True Differential I/O Standards - f_HSDRDPA (data rate)	SERDES factor J = 4 to 10⁴⁶ ⁴⁷ ⁴⁸	150	—	1,600	150	—	1,434	150	—	1,250	150	—	1,000	Mbps
	True Differential I/O Standards - f_HSDRDPA (data rate)	SERDES factor J = 3⁴⁶ ⁴⁷ ⁴⁸	150	—	1,200	150	—	1,076	150	—	938	150	—	600	Mbps
	f_HSDR (data rate) (without DPA)⁴⁵	SERDES factor J = 3 to 10	⁴⁸	—	⁵²	⁴⁸	—	⁵²	⁴⁸	—	⁵²	⁴⁸	—	⁵²	Mbps
		SERDES factor J = 2, uses DDR registers	⁴⁸	—	⁴⁹	⁴⁸	—	⁴⁹	⁴⁸	—	⁴⁹	⁴⁸	—	⁴⁹	Mbps
		SERDES factor J = 1, uses DDR registers	⁴⁸	—	⁴⁹	⁴⁸	—	⁴⁹	⁴⁸	—	⁴⁹	⁴⁸	—	⁴⁹	Mbps
DPA (FIFO mode)	DPA run length	—	—	—	10,000	—	—	10,000	—	—	10,000	—	—	10,000	UI
DPA (soft CDR mode)	DPA run length	SGMII/GbE protocol	—	—	5	—	—	5	—	—	5	—	—	5	UI
DPA (soft CDR mode)	DPA run length	All other protocols	—	—	50 data transition per 208 UI	—	—	50 data transition per 208 UI	—	—	50 data transition per 208 UI	—	—	50 data transition per 208 UI	—
Soft CDR mode	Soft-CDR ppm tolerance	—	–300	—	300	–300	—	300	–300	—	300	–300	—	300	ppm
Non DPA mode	Sampling Window	—	—	—	330	—	—	330	—	—	330	—	—	330	ps

⁴³ Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.

⁴⁴ This is achieved by using the PHY clock network.

⁴⁵ Requires package skew compensation with PCB trace length.

⁴⁶ The F_max specification is based on the fast clock used for serial data. The interface F_max is also dependent on the parallel clock domain which is design dependent and requires timing analysis.

⁴⁷ The V_CC and V_CCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.

⁴⁸ The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.

⁴⁹ The maximum ideal data rate is the SERDES factor (J) × the PLL maximum output frequency (f_OUT) provided you can close the design timing and the signal integrity meets the interface requirements.

⁵⁰ Not applicable for DIVCLK = 1.

⁵¹ This applies to default pre-emphasis and V_OD settings only.

⁵² You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.

DPA Lock Time Specifications

Table 39. DPA Lock Time Specifications for Intel^® Agilex™ Devices
The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1- to-0 transition.

For specification status, see the Data Sheet Status table
Standard	Training Pattern	Number of Data Transitions in One Repetition of the Training Pattern	Number of Repetitions per 256 Data Transitions⁵³	Maximum Data Transition
SPI-4	00000000001111111111	2	128	768
Parallel Rapid I/O	00001111	2	128	768
Parallel Rapid I/O	10010000	4	64	768
Miscellaneous	10101010	8	32	768
Miscellaneous	01010101	8	32	768

⁵³ This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.

LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications

Figure 2. LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps

Table 40. LVDS SERDES Soft-CDR Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps For specification status, see the Data Sheet Status table
Parameter	Jitter Frequency (Hz)	Sinusoidal Jitter (UI)
F1	10,000	25
F2	17,565	25
F3	1,493,000	0.22
F4	50,000,000	0.22

Figure 3. LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps

Memory Standards Supported by the Hard Memory Controller

Table 41. Memory Standards Supported by the Hard Memory Controller for Intel^® Agilex™ Devices
This table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator.

For specification status, see the Data Sheet Status table
Memory Standard	Rate Support	Maximum Frequency (MHz)
DDR4 SDRAM	Quarter rate	1,600

Memory Standards Supported by the Soft Memory Controller

Table 42. Memory Standards Supported by the Soft Memory Controller for Intel^® Agilex™ Devices
This table lists the overall capability of the soft memory controller. For specific details, refer to the External Memory Interface Spec Estimator.

For specification status, see the Data Sheet Status table
Memory Standard	Rate Support	Maximum Frequency (MHz)
QDR IV SRAM	Quarter rate	1,066

Memory Standards Supported by the HPS Hard Memory Controller

Table 43. Memory Standards Supported by the HPS Hard Memory Controller for Intel^® Agilex™ Devices
This table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator.

For specification status, see the Data Sheet Status table
Memory Standard	Rate Support	Maximum Frequency (MHz)
DDR4 SDRAM	Quarter rate	1,600
DDR4 SDRAM	Half rate	1,333

DLL Range Specifications

Table 44. DLL Frequency Range Specifications for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Parameter	Performance (for All Speed Grades)	Unit
DLL operating frequency range	600 – 1,600	MHz
DLL reference clock input	Minimum 600	MHz

Memory Output Clock Jitter Specifications

The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel^® recommends using PHY clock networks for better jitter performance.

The memory clock output jitter is within the JEDEC* specifications when the phase jitter (integration bandwidth 10 kHz to 50 MHz) of the input clock is not more than 20 ps peak-to-peak, or 1.42 ps RMS at 1e^-12 BER and 1.22 ps at 1e^-16 BER.

E-Tile Transceiver Performance Specifications

This section provides E-tile transceiver specifications and timing for Intel^® Agilex™ devices.

E-Tile Transceiver Performance

Table 45. E-Tile Transmitter and Receiver Data Rate Performance Specifications For specification status, see the Data Sheet Status table
Symbol/Description	Condition	Transceiver Speed Grade			Unit
Symbol/Description	Condition	–1	–2	–3	Unit
Supported data rate⁵⁴	NRZ	28.9	28.3	17.4	Gbps
Supported data rate⁵⁴	PAM4	57.8⁵⁵	56	32	Gbps

⁵⁴ The supported data rate is for chip-to-chip and backplane links.

⁵⁵ Two channels are combined to support up to 57.8 Gbps.

E-Tile Transceiver Reference Clock Specifications

Table 46. E-Tile Reference Clock LVPECL DC Electrical Characteristics For specification status, see the Data Sheet Status table
Symbol	Refclk Parameter	Min	Typ	Max	Unit
V_TT	Termination voltage (2.5 V compliant)	0.4	0.5	0.6	V
V_TT	Termination voltage (3.3 V compliant)	1.04	1.3	1.56	V
R_TT	Termination resistor	40	50	60	Ω
V_DIFF	Differential voltage	0.4	0.8	1.2	V
V_CM	Input common mode voltage (2.5 V compliant, no internal termination resistor)	V_DIFF/2	—	V_{CCCLK_GXE}– V_DIFF/2	V
	Input common mode voltage (2.5 V compliant, internal termination resistor)	V_{CCCLK_GXE}– 1.6	V_{CCCLK_GXE}– 1.3	V_{CCCLK_GXE}– 1.0	V
	Input common mode voltage (3.3 V compliant, no internal termination resistor)	V_DIFF/2	—	V_{CCCLK_GXE}– V_DIFF/2	V
	Input common mode voltage (3.3 V compliant, internal termination resistor)	1.4	2	2.6	V

Table 47. E-Tile Reference Clock Electrical and Jitter Requirements For specification status, see the Data Sheet Status table
Parameter	Condition	Min	Typ	Max	Unit
Frequency	—	125	156.25	700	MHz
Frequency tolerance	—	–100	—	100	ppm
Clock duty cycle	—	45	50	55	%
Rise/Fall times	20% to 80%	40	—	300	ps
Phase jitter	12 kHz to 20 MHz	—	0.375	0.5	ps rms
Phase noise⁵⁶	10 kHz	—	—	–130	dBc/Hz
	100 kHz	—	—	–138	dBc/Hz
	500 kHz	—	—	–138	dBc/Hz
	3 MHz	—	—	–140	dBc/Hz
	10 MHz	—	—	–144	dBc/Hz
	20 MHz	—	—	–146	dBc/Hz

⁵⁶ The phase noise numbers in this table are the maximum acceptable phase noise values measured at a carrier frequency of 156.25 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 156.25 MHz + 20*log₁₀(f/156.25).

E-Tile Transmitter Specifications

Table 48. E-Tile Transmitter Specifications For specification status, see the Data Sheet Status table
Symbol/Description	Condition	Min	Typ	Max	Unit
Transmitter differential output voltage peak-to-peak	No precursor/postcursor de-emphasis	—	0.965	—	V
Transmitter common mode voltage	—	V_{CCRT_GXE}/2			V

E-Tile Receiver Specifications

Table 49. E-Tile Receiver Specifications For specification status, see the Data Sheet Status table
Symbol/Description	Condition	Min	Typ	Max	Unit
Absolute V_MAX for a receiver pin	NRZ	—	V_{CCH_GXE} + 0.3	—	V
Absolute V_MAX for a receiver pin	PAM4	—	V_{CCH_GXE}	—	V
Maximum peak-to-peak differential input voltage V_ID (diff p-p) before/after device configuration	—	1.2			V
V_CM (Internal AC coupled)⁵⁷	NRZ	GND	—	V_{CCH_GXE}	V
V_CM (Internal AC coupled)⁵⁷	PAM4	GND + 0.3	—	V_{CCH_GXE} – 0.3	V
Receiver run length⁵⁸	—	—	—	100⁵⁹	symbols
DC input impedance	—	40	—	60	Ω
DC differential input impedance	—	80	100	120	Ω
Powered down DC input impedance	Receiver pin impedance when the receiver termination is powered down	100k	—	—	Ω
Differential termination	From DC to 100 MHz	80	100	120	Ω
PPM tolerance	Allowed frequency mismatch between REFCLK and RX data	—	—	750	ppm

⁵⁷ This value uses internal AC coupling. External coupling capacitors are required beyond the range mentioned in this table.

⁵⁸ No additional transition density requirements apply.

⁵⁹ The incoming data must be statistically DC-balanced.

P-Tile Transceiver Performance Specifications

This section provides P-tile transceiver specifications and timing for Intel^® Agilex™ devices.

P-Tile Transceiver Performance

Table 50. P-Tile Transmitter and Receiver Data Rate Performance For specification status, see the Data Sheet Status table
Symbol/Description	Condition	Gen 1	Gen 2	Gen 3	Gen 4	Unit
Supported data rate	PCIe*	2.5	5	8	16	Gbps

Table 51. P-Tile PLLA Performance For specification status, see the Data Sheet Status table
Symbol/Description	Condition	Transceiver Speed Grade			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
VCO frequency	—	—	5	—	GHz
PLL bandwidth (BWTX-PKG_PLL1)⁶⁰	PCIe* 2.5 GT/s	1.5	—	22	MHz
PLL bandwidth (BWTX-PKG_PLL1)⁶⁰	PCIe* 5.0 GT/s	8	—	16	MHz
PLL bandwidth (BWTX-PKG_PLL2)⁶⁰	PCIe* 5.0 GT/s	5	—	16	MHz
PLL peaking (PKGTX-PLL1)	PCIe* 2.5 GT/s	—	—	3	dB
PLL peaking (PKGTX-PLL1)	PCIe* 5.0 GT/s	—	—	3	dB
PLL peaking (PKGTX-PLL2)⁶⁰	PCIe* 5.0 GT/s	1	—	—	dB

Table 52. P-Tile PLLB Performance For specification status, see the Data Sheet Status table
Symbol/Description	Condition	Transceiver Speed Grade			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
VCO frequency	—	—	8	—	GHz
PLL bandwidth (BWTX-PKG_PLL1)⁶¹	PCIe* 8.0 GT/s	2	—	4	MHz
PLL bandwidth (BWTX-PKG_PLL1)⁶¹	PCIe* 16.0 GT/s	2	—	4	MHz
PLL bandwidth (BWTX-PKG_PLL2)⁶¹	PCIe* 8.0 GT/s	2	—	5	MHz
PLL bandwidth (BWTX-PKG_PLL2)⁶¹	PCIe* 16.0 GT/s	2	—	5	MHz
PLL peaking (PKGTX-PLL1)⁶¹	PCIe* 8.0 GT/s	—	—	2	dB
PLL peaking (PKGTX-PLL1)⁶¹	PCIe* 16.0 GT/s	—	—	2	dB
PLL peaking (PKGTX-PLL2)⁶¹	PCIe* 8.0 GT/s	—	—	1	dB
PLL peaking (PKGTX-PLL2)⁶¹	PCIe* 16.0 GT/s	—	—	1	dB

⁶⁰ The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the –3 dB point.

⁶¹ The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the –3 dB point.

P-Tile Transceiver Reference Clock Specifications

Table 53. P-Tile Reference Clock Specifications For specification status, see the Data Sheet Status table
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O standards	—	HCSL			—
Input reference clock frequency⁶²	—	99.97	100	100.03	MHz
Rising edge rate⁶³	PCIe*	0.6	—	4	V/ns
Falling edge rate⁶³	PCIe*	0.6	—	4	V/ns
Duty cycle	PCIe*	40	—	60	%
Spread-spectrum modulating clock frequency	—	30	—	33	kHz
Spread-spectrum downspread	—	–0.5	—	0	%
Absolute V_MAX	—	—	—	1.15	V
Absolute V_MIN	—	—	—	–0.3	V
Peak-to-peak differential input voltage	—	300	—	1,500	mV
V_ICM (DC coupled)	HCSL I/O standard for PCIe* reference clock	250	—	550	mV
Cycle to cycle jitter (TCCJITTER)⁶⁴	PCIe*	—	—	150	ps
TSSC-MAX-PERIOD-SLEW	Max SSC df/dt	—	—	1,250	ppm/μs

⁶² This number is with spread spectrum clocking (SSC) turned off. For systems with spread spectrum clocking, follow the specifications in Section 8.6.3 Data Rate Independent Refclk Parameters in the PCI Express* Base Specification Revision 4.0.

⁶³ Measured from –150 mV to +150 mV on the differential waveform. The 300 mV measurement window is centered on the differential zero crossing.

⁶⁴ For common reference clock architecture, follow the jitter limit specified in the PCI Express** Card Electromechanical Specification for 2.5 GT/s, Section 4.3.7 Refclk Specifications for 5.0 GT/s and Section 4.3.8 Refclk Specifications for 8.0 GT/s in the PCI Express* Base Specification Revision 3.0, and Section 8.6 Refclk Specifications for 16.0 GT/s in the PCI Express* Base Specification Revision 4.0.

P-Tile Transmitter Specifications

Table 54. P-Tile Transmitter Specifications For specification status, see the Data Sheet Status table
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O standards	PCIe*	High Speed Differential I/O			—
Differential on-chip termination resistors	PCIe*	80	—	120	Ω
Differential peak-to-peak voltage for full swing	PCIe* 2.5 GT/s	800	—	1,100	mV
	PCIe* 5.0 GT/s	800	—	1,100	mV
	PCIe* 8.0 GT/s	800	—	1,100	mV
	PCIe* 16.0 GT/s	800	—	1,100	mV
Differential peak-to-peak voltage during EIEOS	PCIe* 8.0 GT/s and 16.0 GT/s	250	—	—	mV
Lane-to-lane output skew	PCIe* 2.5 GT/s	—	—	2.5	ns
	PCIe* 5.0 GT/s	—	—	2	ns
	PCIe* 8.0 GT/s	—	—	1.5	ns
	PCIe* 16.0 GT/s	—	—	1.25	ns

P-Tile Receiver Specifications

Table 55. P-Tile Receiver Specifications For specification status, see the Data Sheet Status table
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O standards	PCIe*	High Speed Differential I/O			—
Peak-to-peak differential input voltage V_ID (diff p-p)	PCIe* 2.5 GT/s⁶⁵	175⁶⁶	—	1,200	mV
	PCIe* 5.0 GT/s⁶⁵	100⁶⁶	—	1,200	mV
	PCIe* 8.0 GT/s	25⁶⁶	—	—⁶⁷	mV
	PCIe* 16.0 GT/s	15⁶⁶	—	—⁶⁷	mV
Differential on-chip termination resistors	—	80	—	120	Ω
RESREF⁶⁸	—	167.3	169	170.7	Ω
RREF	—	2.772	2.8	2.828	kΩ

⁶⁵ Voltage shown for PCIe* 2.5 GT/s and 5.0 GT/s are at the package pins (TP2).

⁶⁶ For PCIe* at 2.5 GT/s and 5 GT/s, the V_ID is measured at TP2, which is the accessible test point at the device under test. For PCIe* 8.0 GT/s and 16.0 GT/s, the V_ID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined.

⁶⁷ The maximum eye height value depends on the transmitter launch voltage maximum value. Refer to the PCIe* Express Base Specification Rev. 4.0 for the generator (TX) launch voltage value.

⁶⁸ Connecting RESREF at 169 Ω calibrates PCIe* channel on-chip termination to 85 Ω.

R-Tile Transceiver Performance Specifications

R-Tile Transceiver Performance

Table 56. R-Tile Transmitter and Receiver Data Rate Performance for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol/Description	Condition	Transceiver Speed Grade										Unit
		–1					–2
		Gen1	Gen2	Gen3	Gen4	Gen5	Gen1	Gen2	Gen3	Gen4	Gen5
Supported data rate	PCIe*	2.5	5	8	16	32	2.5	5	8	16	32	Gbps
Supported data rate	CXL	—	—	8	16	32	—	—	—	—	—	Gbps

Table 57. R-Tile Slow PLL Performance for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
VCO frequency	PCIe*	—	10	—	GHz
VCO frequency	CXL	—	—	—	GHz
PLL bandwidth (BWTX-PKG_PLL1)⁶⁹	PCIe* 2.5 GT/s	1.5	—	22	MHz
	PCIe* 5.0 GT/s	8	—	16	MHz
	CXL 2.5 GT/s	—	—	—	MHz
	CXL 5.0 GT/s	—	—	—	MHz
PLL bandwidth BWTX-PKG_PLL2)⁶⁹	PCIe* 2.5 GT/s	—	—	—	MHz
	PCIe* 5.0 GT/s	5	—	16	MHz
	CXL 2.5 GT/s	—	—	—	MHz
	CXL 5.0 GT/s	—	—	—	MHz
PLL peaking (PKGTX-PLL1)⁶⁹	PCIe* 2.5 GT/s	—	—	3	dB
	PCIe* 5.0 GT/s	—	—	3	dB
	CXL 2.5 GT/s	—	—	—	dB
	CXL 5.0 GT/s	—	—	—	dB
PLL peaking (PKGTX-PLL2)⁶⁹	PCIe* 2.5 GT/s	—	—	—	dB
	PCIe* 5.0 GT/s	1	—	—	dB
	CXL 2.5 GT/s	—	—	—	dB
	CXL 5.0 GT/s	—	—	—	dB

Table 58. R-Tile Fast PLL Performance for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
VCO frequency	PCIe*	—	16	—	GHz
VCO frequency	CXL	—	16	—	GHz
PLL bandwidth (BWTX-PKG_PLL1)⁷⁰	PCIe* 8.0 GT/s	0.5	—	4	MHz
	PCIe* 16.0 GT/s	0.5	—	4	MHz
	PCIe* 32.0 GT/s	0.5	—	1.8	MHz
	CXL 8.0 GT/s	0.5	—	4	MHz
	CXL 16.0 GT/s	0.5	—	4	MHz
	CXL 32.0 GT/s	0.5	—	1.8	MHz
PLL bandwidth (BWTX-PKG_PLL2)⁷⁰	PCIe* 8.0 GT/s	0.5	—	5	MHz
	PCIe* 16.0 GT/s	0.5	—	5	MHz
	PCIe* 32.0 GT/s	—	—	—	—
	CXL 8.0 GT/s	0.5	—	5	MHz
	CXL 16.0 GT/s	0.5	—	5	MHz
	CXL 32.0 GT/s	—	—	—	—
PLL peaking (PKGTX-PLL1)⁷⁰	PCIe* 8.0 GT/s	—	—	2	dB
	PCIe* 16.0 GT/s	—	—	2	dB
	PCIe* 32.0 GT/s	—	—	2	dB
	CXL 8.0 GT/s	—	—	2	dB
	CXL 16.0 GT/s	—	—	2	dB
	CXL 32.0 GT/s	—	—	2	dB
PLL peaking (PKGTX-PLL2)⁷⁰	PCIe* 8.0 GT/s	—	—	1	dB
	PCIe* 16.0 GT/s	—	—	1	dB
	PCIe* 32.0 GT/s	—	—	—	—
	CXL 8.0 GT/s	—	—	1	dB
	CXL 16.0 GT/s	—	—	1	dB
	CXL 32.0 GT/s	—	—	—	—

⁶⁹ The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the –3 dB point.

⁷⁰ The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the –3 dB point.

R-Tile Transceiver Reference Clock Specifications

Table 59. R-Tile Reference Clock Specifications for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O standards	PCIe*	HCSL			—
Supported I/O standards	CXL	HCSL			—
Refclk frequency for devices that support 32.0 GT/s⁷¹	PCIe*	99.99	100	100.01	MHz
Refclk frequency for devices that support 32.0 GT/s⁷¹	CXL	99.99	100	100.01	MHz
Rising edge rate⁷²	PCIe*	0.6	—	4	V/ns
Rising edge rate⁷²	CXL	0.6	—	4	V/ns
Falling edge rate⁷²	PCIe*	0.6	—	4	V/ns
Falling edge rate⁷²	CXL	0.6	—	4	V/ns
Duty cycle	PCIe*	40	—	60	%
Duty cycle	CXL	40	—	60	%
Absolute V_MAX	PCIe*	—	—	1.15	V
Absolute V_MAX	CXL	—	—	1.15	V
Absolute V_MIN	PCIe*	—	—	–0.3	V
Absolute V_MIN	CXL	—	—	–0.3	V
Peak-to-peak differential input voltage	PCIe*	300	—	1,450	mV
Peak-to-peak differential input voltage	CXL	300	—	1,450	mV
Vcross	PCIe*	250	—	550	mV
Vcross	CXL	250	—	550	mV
Cycle-to-cycle jitter (T_CCJITTER)⁷³	PCIe*	—	—	150	ps
Cycle-to-cycle jitter (T_CCJITTER)⁷³	CXL	—	—	150	ps
Spread-spectrum modulating clock frequency	PCIe*	30	—	33	kHz
Spread-spectrum modulating clock frequency	CXL	30	—	33	kHz
SSC deviation for devices that support 32.0 GT/s and SRIS when operating in SRIS mode at all speeds	PCIe*	–0.3	—	0	%
	CXL	–0.3	—	0	%
T_{SSC-MAX-PERIOD-SLEW}	Max SSC df/dt for PCIe*	—	—	1,250	ppm/µs
T_{SSC-MAX-PERIOD-SLEW}	Max SSC df/dt for CXL	—	—	1,250	ppm/µs

⁷¹ This number is with spread-spectrum clocking (SSC) turned off. For systems with spread spectrum clocking, follow the specifications in Section 8.6 Refclk Specifications of PCI Express* Base Specification Revision 5.0 Version 1.0.

⁷² Measured from –150 mV to +150 mV on the differential waveform. The 300 mV measurement window is centered on the differential zero crossing.

⁷³ For common reference clock architecture, you must meet the jitter limit specified in Section 8.6 Refclk Specifications of PCI Express* Base Specification Revision 5.0 Version 1.0.

R-Tile Transmitter Specifications

Table 60. R-Tile Transmitter Specifications for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O standards	PCIe*	High-Speed Differential I/O			—
Supported I/O standards	CXL	High-Speed Differential I/O			—
Differential on-chip termination resistors	PCIe*	80	100	120	Ω
Differential on-chip termination resistors	CXL	80	100	120	Ω
Differential peak-to-peak voltage for full swing	PCIe* 2.5 GT/s	800	—	1,200	mV
	PCIe* 5.0 GT/s	800	—	1,200	mV
	PCIe* 8.0 GT/s	800	—	1,300	mV
	PCIe* 16.0 GT/s	800	—	1,300	mV
	PCIe* 32.0 GT/s	800	—	1,300	mV
	CXL 8.0 GT/s	800	—	1,300	mV
	CXL 16.0 GT/s	800	—	1,300	mV
	CXL 32.0 GT/s	800	—	1,300	mV
Differential peak-to-peak voltage during EIEOS	PCIe* 8.0 GT/s, 16.0 GT/s, and 32.0 GT/s	250	—	—	mV
Differential peak-to-peak voltage during EIEOS	CXL 8.0 GT/s, 16.0 GT/s, and 32.0 GT/s	250	—	—	mV
Lane-to-lane output skew	PCIe* 2.5 GT/s	—	—	2.5	ns
	PCIe* 5.0 GT/s	—	—	2	ns
	PCIe* 8.0 GT/s	—	—	1.5	ns
	PCIe* 16.0 GT/s	—	—	1.25	ns
	PCIe* 32.0 GT/s	—	—	1.25	ns
	CXL 8.0 GT/s	—	—	1.5	ns
	CXL 16.0 GT/s	—	—	1.25	ns
	CXL 32.0 GT/s	—	—	1.25	ns

R-Tile Receiver Specifications

Table 61. R-Tile Receiver Specifications for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O standards	PCIe*	High-Speed Differential I/O			—
Supported I/O standards	CXL	High-Speed Differential I/O			—
Peak-to-peak differential input voltage V_ID (diff p-p)	PCIe* 2.5 GT/s⁷⁴	175	—	1,200	mVPP
	PCIe* 5.0 GT/s⁷⁴	100	—	1,200	mVPP
	PCIe* 8.0 GT/s⁷⁴	25	—	1,200	mVPP
	PCIe* 16.0 GT/s⁷⁴	15	—	800	mVPP
	PCIe* 32.0 GT/s⁷⁴	15	—	800	mVPP
	CXL 8.0 GT/s⁷⁴	25	—	1,200	mVPP
	CXL 16.0 GT/s⁷⁴	15	—	800	mVPP
	CXL 32.0 GT/s⁷⁴	15	—	800	mVPP
Differential on-chip termination resistors	PCIe*	80	100	120	Ω
Differential on-chip termination resistors	CXL	80	100	120	Ω
RCOMP	PCIe* ⁷⁵	148.5	150	151.5	Ω
RCOMP	CXL⁷⁵	148.5	150	151.5	Ω

⁷⁴ For PCIe* at 2.5 GT/s and 5 GT/s, V_ID is measured at TP2, which is the accessible test point at the device under test. For PCIe* and CXL 8.0 GT/s, 16.0 GT/s and 32.0 GT/s, V_ID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined.

⁷⁵ Connecting RCOMP at 150 Ω calibrates PCIe* and CXL channel on-chip termination to 100 Ω.

F-Tile Transceiver Performance Specifications

F-Tile Transceiver Performance

Table 62. F-Tile FHT Transmitter and Receiver Data Rate Performance for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol/Description	Condition	Transceiver Speed Grade			Unit
Symbol/Description	Condition	–1	–2	–3	Unit
Supported data rate	NRZ	24–29, 48–58	24–29	24–29	Gbps
Supported data rate	PAM4	48–58, 96–116	48–58	48–58	Gbps

Table 63. F-Tile FGT Transmitter and Receiver Data Rate Performance for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol/Description	Condition	Transceiver Speed Grade			Unit
Symbol/Description	Condition	–1	–2	–3	Unit
Supported data rate	NRZ	1–32	1–32	1–17.4	Gbps
Supported data rate	PAM4	20–58.125	20–58.125	20–32	Gbps

F-Tile Transceiver Reference Clock Specifications

Table 64. F-Tile FHT Reference Clock Requirements for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Parameter	Description	Condition	Min	Typical	Max	Unit
Frequency	Reference clock frequency	—	100	100	200	MHz
Frequency	Reference clock frequency	—	100	156.25	200	MHz
Frequency accuracy	Frequency accuracy of the reference clock, including temperature variability, aging, and initial variation	—	—	—	±100	ppm
Single sideband phase noise	Measured SSB phase noise must be smaller than phase noise mask⁷⁶	10 kHz	—	–130	—	dB
		100 kHz	—	–138	—	dB
		500 kHz	—	–138	—	dB
		3 MHz	—	–140	—	dB
		10 MHz	—	–144	—	dB
		20 MHz	—	–146	—	dB
		1 GHz	—	–146 ⁷⁷	—	dB
Integrated RMS jitter	Integrated over 10 kHz – 20 MHz, include spurious	—	—	—	522	fs

Table 65. F-Tile FHT Reference Clocks Input Specifications for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Parameter	Description	Condition	Min	Typical	Max	Unit
T_REF-DUTY	Duty cycle	—	45	50	55	%
T_{REF-RISE/FALL}	Rising and falling edge rate	20% – 80%	40	—	300	ps
T_{REF-SINGLEEND-SKEW}	Skew between REFCLKP and REFCLKN	—	—	—	5	ps
Z_{REF-SINGLEEND-DC}	Reference clock input impedance – terminated mode	—	40	50	60	Ω
V_REFIN-SE-PP	Input reference clock single-ended peak-to-peak voltage	—	200	—	510	mV
V_REFIN-CM-AC	Input reference clock common-mode voltage when AC-coupled on board	—	Set on-chip			—
V_REFIN-IL-DC	Input reference clock input low voltage when DC-coupled on board	—	0.1	—	—	V
V_REFIN-IH-DC	Input reference clock input high voltage when DC-coupled on board	—	—	—	0.9	V

Table 66. F-Tile FGT Reference Clock Input Specifications for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Parameter	Description	Condition	Min	Typical	Max	Unit
F_REF	Reference clock operating frequency	—	100	—	380	MHz
T_REF-DUTY	Duty cycle	—	45	50	55	%
T_{REF-RISE/FALL}	Rising and falling edge rate	20% – 80%	—	—	0.15	T_REF
T_{REF-SINGLEEND-SKEW}	Skew between REFCLKP and REFCLKN	—	—	—	50	ps
Z_REF-DIFF-DC	Reference clock differential input impedance – terminated mode	—	80	100	120	Ω
V_{REFIN-DIFF-AC}	Input reference clock differential peak-to-peak voltage when AC-coupled on board	—	0.6	1.2	1.7	V_pp-diff
V_REFIN-IL-DC	Input reference clock input low voltage when DC-coupled on board	—	–0.15	0	0.15	V
V_REFIN-IH-DC	Input reference clock input high voltage when DC-coupled on board	—	0.66	0.7	0.85	V
PN_REF-SSB	Reference clock measured single sideband phase noise mask including spurs must be smaller than phase noise mask⁷⁸	10 kHz	—	–130	—	dBc/Hz
		100 kHz	—	–138	—	dBc/Hz
		500 kHz	—	–138	—	dBc/Hz
		3 MHz	—	–140	—	dBc/Hz
		10 MHz	—	–144	—	dBc/Hz
		20 MHz	—	–146	—	dBc/Hz
		1 GHz	—	–146	—	dBc/Hz
V_REFIN-RJ-RMS	RMS jitter integrated from 10 kHz – 20 MHz including spurs	—	—	—	522	fs
V_{REFIN-PPM-ERROR}	Reference clock frequency error	—	–350 + SSC	—	+350 + SSC	ppm

Table 67. F-Tile FGT Reference Clock Output Driver Specifications for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Parameter	Description	Condition	Min	Typical	Max	Unit
F_{REF_OUT}	Reference clock operating frequency	—	25	—	800	MHz
T_{REF-DUTY_OUT}	Duty cycle	—	45	50	55	%
T_{REF-RISE_OUT/FALL_OUT}	Rising and falling edge rate	20% – 80%	—	—	0.15	T_REF
T_{REF-SINGLEEND-SKEW}	Skew between REFCLKP and REFCLKN	—	—	—	50	ps
Z_{REF-DIFF-DC_OUT}	Reference clock differential input impedance – terminated mode	—	80	100	120	Ω
V_{REFIN-DIFF-AC_OUT}	Input reference clock differential peak to peak voltage when AC-coupled on board	—	0.9	1	1.1	V_pp-diff
V_REFIN-CM-OUT	Output reference clock common-mode	—	0.45	0.5	0.55	V

⁷⁶ Add an offset of 20 × log10(F_clk/156.25 MHz) dB to mask values, where F_clk is reference clock frequency.

⁷⁷ The phase noise mask requirement between 20 MHz and 1 GHz excludes any harmonics power of the fundamental clock.

⁷⁸ Add an offset of 20 × log10(Fcc/Hzlk/156.25 MHz) dB to mask values, where F_clk is reference clock frequency.

F-Tile Transmitter Specifications

Table 68. F-Tile FHT Transmitter Electrical Specifications For specification status, see the Data Sheet Status table
Parameter	Symbol	Description	Min	Typical	Max	Unit
Output eye specifications	V_TX-DIFF-PKPK	Transmit amplitude (low frequency)	800	—	1,200	mV_diff-pkpk
	V_{TX-DEEMP_STEP}	Transmit tap resolution for c(0), c(1), and c(–1)	0.5	—	5	%
	V_{TX-DEEMP_STEP}	Transmit tap resolution for c(–2)	0.5	—	2.5	%
	T_TX-SLEW	Rise/fall time	8	—	—	ps
	T_TX-DJ	Even-odd jitter	—	—	0.023	UI_pkpk
	T_TX-RJ	J3u⁷⁹	—	—	0.106	UI_pkpk
	T_TX-RJ	JRMS⁷⁹	—	—	0.023	UI_RMS
	N_GPLL	Ratio of the F_3DB cutoff frequency for the 1st order high-pass jitter measurement filter, to the data rate	—	28,000	—	F_BAUD/F_GPLL
Transmitter DC impedance	Z_TX-DIFF-DC	Transmitter output differential DC impedance 100 W mode while configured	80	100	120	W
Transmitter DC impedance	Z_TX-CM-DC	Transmitter output common-mode DC impedance	20	25	30	W
Transmitter return loss	Z_RL-DIFF-DC	Transmitter differential DC return loss	—	—	–14.5	dB
	Z_RL-DIFF-NYQ	Transmitter differential return loss at Nyquist frequency (F_BAUD/2)	—	—	–8	dB
	Z_RL-CMN	Transmitter common-mode return loss below 10 GHz	—	—	–6	dB
Electrical idle	V_TX-IDLE	Idle output voltage	—	—	50	mV_pkpk
	V_{CM-DELTA-SQUELCH}	Maximum common-mode step entering/exiting squelch mode	—	—	100	mV
	T_{TX-IDLE-LATENCY}	Latency entering/exiting idle (cold boot)	—	—	28	ms
	T_{TX-IDLE-LATENCY}	Power state cycle (re-establish CM)	—	—	5	µs

Table 69. F-Tile FGT Transmitter Electrical Specifications For specification status, see the Data Sheet Status table
Parameter	Symbol	Description	Min	Typical	Max	Unit
Output eye specifications	V_TX-DIFF-PKPK	Transmit amplitude	300	—	1,050	mV_diff-pkpk
	V_{TX-DEEMP_STEP}	Transmit tap resolution	—	—	2	%
	D_TX-N+2-DEEMP	N+2 precursor tap de-emphasis	0	—	2.5	dB
	D_TX-N+1-DEEMP	N+1 precursor tap de-emphasis	0	—	4.5	dB
	D_TX-N-1-DEEMP	N-1 postcursor tap de-emphasis	0	—	6.5	dB
	T_TX-SLEW	Rise/fall time at 10%–90% or 20%–80%	10	—	20	ps
	T_TX-DJ	Transmit deterministic jitter at 25 Gbps	—	—	0.15	UI_pkpk
	T_TX-RJ	Transmit total peak-peak random jitter⁸⁰	—	—	0.15	UI_pkpk
	T_TX-TJ	Transmit total peak-peak jitter (T_TX-TJ = T_TX-DDJ + T_TX-PJ + T_TX-RJ)⁸⁰	—	—	0.28	UI_pkpk
	N_GPLL-PAM	Ratio of the F_3DB cutoff frequency for the 1st order high-pass jitter measurement filter for PAM modulation, to the data rate	—	6,640	—	F_BAUD/F_GPLL-PAM
	N_GPLL-NRZ	Ratio of the F_3DB cutoff frequency for the 1st order high-pass jitter measurement filter for NRZ modulation, to the data rate	—	2,578	—	F_BAUD/F_GPLL-NRZ
Transmitter DC impedance	Z_TX-DIFF-DC	Transmitter output differential DC impedance 100 W mode while configured⁸¹	80	100	120	W
Transmitter DC impedance	Z_TX-CM-DC	Transmitter output common-mode DC impedance	20	25	30	W
Transmitter return loss	Z_RL-DIFF-DC	Transmitter differential DC return loss	—	—	12	dB
	Z_RL-DIFF-NYQ	Transmitter differential return loss at Nyquist frequency (F_BAUD/2)	—	—	–6	dB
	Z_RL-CMN	Transmitter common-mode return loss below 10 GHz	—	—	–6	dB
Electrical idle	V_TX-IDLE	Idle output voltage	—	—	20	mV_pkpk
	V_{CM-DELTA-SQUELCH}	Maximum common-mode step entering/exiting squelch mode	—	—	100	mV
	T_{TX-IDLE-LATENCY}	Latency entering/exiting idle (cold boot), power state cycle (re-establish CM)	—	—	8	µs
Receiver detect	V_{TX-RCV-DETECT}	Voltage change allowed during receiver detection	—	—	600	mV
Lane-to-lane output skew	—	Lane count ≤ 8	—	—	2 UI + 200 ps	ps
Lane-to-lane output skew	—	Lane count = 16	—	—	2 UI + 300 ps	ps

⁷⁹ CDR bandwidth is at 4 MHz.

⁸⁰ Assume a 1^st order high-pass jitter measurement filter with a cutoff of F_baud/F_gpll = N_gpll.

⁸¹ TX pins are driven to 0 V before mode configuration.

F-Tile Receiver Specifications

Table 70. F-Tile FHT Receiver Electrical Specifications For specification status, see the Data Sheet Status table
Parameter	Symbol	Description	Min	Typical	Max	Unit
Receiver input eye specifications	V_RX-DIFF-PKPK	Receiver input differential peak-to-peak voltage	Closed eye	—	1,200	mV_diff-pkpk
	V_RX-CM-DC	Receiver input DC common-mode voltage⁸²	100	750	900	mV
	T_RX-DDJ	Receive input signal data dependent jitter (inter-symbol interference)	—	—	1	UI_pkpk
	T_RX-RJ	Receive input random jitter	—	—	0.15	UI_pkpk
	T_RX-PJ	Receive input periodic jitter (at high frequency)	—	—	0.05	UI_pkpk
	T_RX-TJ	Receive input total jitter (DDJ + RJ + PJ)	—	—	1	UI_pkpk
	N_GPLL	Ratio of the F_3DB cutoff frequency for the 1st order high-pass jitter measurement filter, to the data rate	—	28,000	—	F_BAUD/F_GPLL
Equalizer specifications	F_PPM-OFFSET	Tolerable data frequency offset	–200	—	200	ppm
Receiver return loss	Z_RL-DIFF-DC	Receiver differential DC return loss	—	—	–10	dB
	Z_RL-DIFF-NYQ	Receiver differential return loss at Nyquist frequency (F_BAUD/2)	—	—	–6	dB
	Z_RL-CM	Receiver common-mode return loss below 10 GHz	—	—	–6	dB
Receiver DC impedance	R_DIFF-DC	DC differential receive impedance	80	100	120	W
Receiver DC impedance	R_CM-DC	DC common-mode receive impedance	20	25	30	W

Table 71. F-Tile FGT Receiver Electrical Specifications For specification status, see the Data Sheet Status table
Parameter	Symbol	Description	Min	Typical	Max	Unit
Receiver input eye specifications	V_RX-DIFF-PKPK	Receiver input differential peak-to-peak voltage	—	—	1,200	mV_diff-pkpk
	V_RX-MAX	Receiver input maximum voltage	—	—	1	V
	V_RX-CM-DC	Receiver input DC common-mode voltage⁸³	0	—	700	mV
	T_RX-RJ	Receive input random jitter	—	—	0.15	UI_pkpk
	T_RX-PJ	Receive input periodic jitter (at high frequency)	—	—	0.05	UI_pkpk
	N_GPLL-PAM	Ratio of the F_3DB cutoff frequency for the 1st order high-pass jitter measurement filter used for PAM modulation, to the data rate	—	6,640	—	F_BAUD/F_GPLL
	N_GPLL-NRZ	Ratio of the F_3DB cutoff frequency for the 1st order high-pass jitter measurement filter for NRZ modulation, to the data rate	—	2,578	—	F_BAUD/F_GPLL-NRZ
Insertion loss specifications	I_{INS-LOSS-56Gb/s}	Insertion loss at 56 Gbps PAM42/BER <10^–4	—	—	30	dB
	I_{INS-LOSS-53Gb/s}	Insertion loss at 53 Gbps PAM42/BER <10^–4	5⁸⁴	—	—	dB
	I_{INS-LOSS-30Gb/s}	Insertion loss at 32 Gbps NRZ⁸⁵ /BER <10^–12	—	—	30	dB
	I_{INS-LOSS-25Gb/s}	Insertion loss at 25.78125 Gbps NRZ⁸⁵/ BER <10^–12	—	—	30	dB
Receiver return loss	Z_RL-DIFF-DC	Receiver differential DC return loss	—	—	–12	dB
	Z_RL-DIFF-NYQ	Receiver differential return loss at Nyquist frequency (F_BAUD/2)	—	—	–6	dB
	Z_RL-CM	Receiver common-mode return loss below 10 GHz	—	—	–6	dB
Receiver DC impedance	R_DIFF-DC	DC differential receive impedance	80	100	120	W
Receiver DC impedance	R_CM-DC	DC common-mode receive impedance	20	25	30	W
Receiver signal detection	V_IDLE-THRESH	Receiver signal detect input voltage threshold	75	120	175	mV_diff-pkpk

⁸² Referenced to RX GND. This specification is also supported before mode configuration.

⁸³ The specified common-mode range is supported when the receiver is powered and configured, powered and unconfigured, or unpowered. This specification is also supported before mode configuration.

⁸⁴ The minimum insertion loss specification assumes a PAM4 transmitter with 800 mVppd. For transmitters with output amplitude adjustment capabilities and can reduce output amplitude to below 800 mVppd, this minimum insertion loss can be further relaxed.

⁸⁵ 2COM compliant package and channel.

F-Tile Electrical Compliance

Table 72. F-Tile FHT Electrical Compliance List For specification status, see the Data Sheet Status table
Specification/Clause	Protocol	Encoding	Lane Rate (Gbps)
IEEE 802.3bs 120D/120E	400GAUI-4	PAM4	106.25
	200GAUI-2	PAM4	106.25
	200GAUI-4	PAM4	53.125
IEEE 802.3cd 135G/135F	100GAUI-1	PAM4	106.25
	100GAUI-2	PAM4	53.125
	100GAUI-4	NRZ	25.78125
	50GAUI-1	PAM4	53.125
	50GAUI-2	NRZ	25.78125
IEEE 802.3cd 109A/109B	25GAUI-1	NRZ	25.78125
IEEE 802.3ck 163/162	400GBASE-KR4/CR4	PAM4	106.25
	200GBASE-KR2/CR2	PAM4	106.25
	100GBASE-KR/CR	PAM4	106.25
IEEE 802.3cd 137/136	200GBASE-KR4/CR4	PAM4	53.125
	100GBASE-KR2/CR2	PAM4	53.125
	50GBASE-KR/CR	PAM4	53.125
IEEE 802.3bj/bm 93 IEEE 802.3bj/bm 92	100GBASE-KR4	NRZ	25.78125
IEEE 802.3bj/bm 93 IEEE 802.3bj/bm 92	100GBASE-CR4	NRZ	25.78125
IEEE 802.3by 111/110	25GBASE-KR/CR	NRZ	25.78125
CEI 4.0/5.0	OIF-CEI-112G XSR/VSR/MR/LR	PAM4	96 – 116
	OIF-CEI-56G VSR/MR/LR	PAM4	48 – 58
	OIF-CEI-28G VSR/SR/MR	NRZ	24 – 29
	OIF-25G LR	NRZ	24 – 29

Table 73. F-Tile FGT Electrical Compliance List For specification status, see the Data Sheet Status table
Specification/Clause	Protocol	Encoding	Lane Rate (Gbps)
IEEE 802.3bs 120D/120E	400GAUI-8	PAM4	53.125
	400GAUI-16	NRZ	26.5625
	200GAUI-4	PAM4	53.125
	200GAUI-8	NRZ	26.5625
IEEE 802.3cd 135G/135F	100GAUI-2	PAM4	53.125
	100GAUI-4	NRZ	25.78125
	50GAUI-1	PAM4	53.125
	50GAUI-2	NRZ	26.5625
IEEE 802.3cd 109A/109B	25GAUI-1	NRZ	25.78125
IEEE 802.3cd 137/136	200GBASE-KR4/CR4	PAM4	53.125
	100GBASE-KR2/CR2	PAM4	53.125
	50GBASE-KR/CR	PAM4	53.125
IEEE 802.3bj/bm 93 IEEE 802.3bj/bm 92	100GBASE-KR4	NRZ	25.78125
IEEE 802.3bj/bm 93 IEEE 802.3bj/bm 92	100GBASE-CR4	NRZ	25.78125
IEEE 802.3bj/ba 85 IEEE 802.3bj/ba 84	40GBASE-KR4	NRZ	10.3125
IEEE 802.3bj/ba 85 IEEE 802.3bj/ba 84	40GBASE-CR4	NRZ	10.3125
IEEE 802.3ap 2007	10GBASE-KR/CR	NRZ	10.3125
IEEE 802.3ap 2008	10GBASE-KX4	NRZ	10.3125
IEEE 802.3by 111/110	25GBASE-KR/CR	NRZ	25.78125
CEI 4.0	CEI-56G VSR/MR/LR	PAM4	36 – 58
	CEI-28G VSR/SR/MR	NRZ	19.9 – 28.1
	IOF-CEI-25G LR	NRZ	19.9 – 28.1
	CEI-11G SR/MR/LR	NRZ	9.95 – 11.2
	CEI-6G SR/LR	NRZ	4.976 – 6.375
G.709 G.sup56 G.sup43 G.sup58	OTU0	NRZ	1.327451
	OTU1	NRZ	2.666057
	OTU1e	NRZ	11.049107
	OTU2/2e	NRZ	10.709225/11.095728
	OTU2f	NRZ	11.317642
	OTU2r	NRZ	12.639086
	OTU3	NRZ	4x10.754603
	OTU4(OTL4.4)	NRZ	4x27.952493
	OTU4(OTL4.10)	NRZ	10x11.180997
G.709.1	100G FlexO-SR (FOIC1.4)	NRZ	4x27.952369
	100G FlexO-SR (FOIC1.2)	PAM4	2x55.904737
	100G FlexO-SR (FOIC2.4)	PAM4	4x55.904737
	100G FlexO-SR (FOIC4.8)	PAM4	8x55.904737
G.709, G.709.4	OTU25u	NRZ	25.781651
	OTU25	NRZ	27.952.493
	OTU50u (OTU50u.2-RS)	NRZ	2x26.562.914
	OTU50u (OTU50u.1-RS)	PAM4	53.125827
	OTU50 (OTU50.2-RS)	NRZ	2x27.952493
	OTU50	PAM4	55.904987
PCIE BASE 4.0	PCIE	NRZ	2.5, 5, 8, 16
SMPTE ST-2081 6G SMPTE ST-2082 12G	SDI	NRZ	0.27, 1.485, 2.970, 5.94, 11.88
CPRI V7.0	CPRI	NRZ	1.2288
		NRZ	2.4576
		NRZ	3.072
		NRZ	4.9152
		NRZ	6.144
		NRZ	8.11008
		NRZ	9.8304
		NRZ	10.1376
		NRZ	12.16512
		NRZ	24.33024
JESD204A/204B/204C	JESD204A/204B/204C	NRZ	12.5 – 16/32
DP 2.0	DisplayPort 2.0	NRZ	1.62, 2.7, 5.4, 8.1, 10, 13.5, 20
FC-PI-4	Fiber Channel	NRZ	1.0625, 2.125, 4.25, 8.5, 10.52, 14.025, 28.05, 57.8
Serial ATA revision 3.0	Sata Gen 1, 2, 3	NRZ	1, 3, 6
T10/BSR INCITS 519	SAS 1, 2, 3, 4	NRZ	3, 6, 12, 22.5
IEEE 802.3av	10G-EPON	NRZ	10
IEEE 802.3ah	1G-EPON	NRZ	1
OIF-28G MR (OIF-CEI3.0)	Interlaken	NRZ	28
OIF-CEI 56G PAM4-MR	Interlaken	PAM4	56
JESD204C	SerialLite IV	NRZ	32
HDMI	HDMI 2.1	NRZ	1.65 – 12
SFF8431	SFP+	NRZ	9.8304 – 12.5
ITU-T G.8261 and G.8262	SyncE	NRZ/PAM4	10, 25, 50
InfiniBand™ Architecture Specification	InfiniBand	NRZ	5, 10, 14.062, 25.78125
RapidIO™ Interconnect Specification	SRIO	NRZ	1.25, 2.5, 3.125, 6.25, 10.3125

HPS Performance Specifications

This section provides hard processor system (HPS) specifications and timing for Intel^® Agilex™ devices.

HPS Clock Performance

Table 74. Maximum HPS Clock Frequencies for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Performance	V_{CCL_HPS} (V)	MPU Frequency (MHz)	L3 Frequency (MHz) (l3_main_free_clk)	MPFE Frequency (MHz)	Rate	DDR Clock (MHz)	DDR (Mb/s per pin)
–1 speed grade	Fixed: 0.95	1,500	400	400	Quarter	1,600	3,200
	Fixed: 0.95	1,500	400	667	Half	1,333	2,666
	SmartVID	1,350	400	400	Quarter	1,600	3,200
	SmartVID	1,350	400	667	Half	1,333	2,666
–2 speed grade	SmartVID	1,200	400	334	Quarter	1,333	2,666
–2 speed grade	SmartVID	1,200	400	600	Half	1,200	2,400
–3 speed grade	SmartVID	1,000	400	300	Quarter	1,200	2,400
–3 speed grade	SmartVID	1,000	400	534	Half	1,067	2,133
–4 speed grade	Fixed: 0.8	1,000	400	267	Quarter	1,067	2,133
–4 speed grade	Fixed: 0.8	1,000	400	467	Half	933	1,866

HPS Internal Oscillator Frequency

Table 75. HPS Internal Oscillator Frequency for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Description	Min	Typ	Max	Unit
Internal oscillator frequency	150	300	400	MHz

HPS PLL Specifications

Table 76. HPS PLL Input Requirements for Intel^® Agilex™ Devices
The main HPS PLL receives its clock signals from the `HPS_OSC_CLK` pin. Refer to the Intel^® Agilex™ Device Family Pin Connection Guidelines for information about assigning this pin.

For specification status, see the Data Sheet Status table
Description	Min	Typ	Max	Unit
Clock input range	25	—	125	MHz
Clock input accuracy	—	—	50	ppm
Clock input duty cycle	45	50	55	%

Table 77. HPS PLL Performance for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Description	Min	Max	Unit
Main PLL VCO output	—	3,000	MHz
Peripheral PLL VCO output	—	3,000	MHz
h2f_user0_clk⁸⁶	—	500	MHz
h2f_user1_clk⁸⁶	—	500	MHz

⁸⁶ The HPS PLL provides this clock to the FPGA fabric.

HPS Cold Reset

Table 78. HPS Cold Reset for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Min	Max	Unit
t_RST0	Minimum time for `HPS_COLD_nRESET` asserted⁸⁷	3	—	ms

⁸⁷ HPS_COLD_nRESET may be ignored if HPS is not running or if the device is being configured.

HPS SPI Timing Characteristics

Table 79. SPI Master Timing Requirements for Intel^® Agilex™ Devices
You can adjust the input delay timing by programming the `rx_sample_dly` register.

For specification status, see the Data Sheet Status table
Symbol	Description	Min	Typ	Max	Unit
T_{spi_ref_clk}	The period of the SPI internal reference clock, sourced from `l4_main_clk`	2.5	—	—	ns
T_clk	SPIM_CLK clock period	16.67	—	—	ns
T_dutycycle	SPIM_CLK duty cycle	45	50	55	%
T_{ck_jitter}	SPIM_CLK output jitter	—	—	2	%
T_dio	Master-out slave-in (MOSI) output skew	–3	—	2	ns
T_dssfrst ⁸⁸	SPI_SS_N asserted to first SPIM_CLK edge	(1.5 × T_clk) – 2	—	—	ns
T_dsslst ⁸⁸	Last SPIM_CLK edge to SPI_SS_N deasserted	T_clk – 2	—	—	ns
T_su ⁸⁹	SPIM_MISO setup time with respect to SPIM_CLK capture edge	5.0 – (`rx_sample_dly` × T_{spi_ref_clk})⁹⁰	—	—	ns
T_h ⁸⁹	Input hold in respect to SPIM_CLK capture edge	1.3 + (`rx_sample_dly` × T_{spi_ref_clk})	—	—	ns

Figure 4. SPI Master Output Timing Diagram

Figure 5. SPI Master Input Timing Diagram

Table 80. SPI Slave Timing Requirements for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Min	Typ	Max	Unit
T_{spi_ref_clk}	The period of the SPI internal reference clock, sourced from `l4_main_clk`	2.5	—	—	ns
T_clk	SPIM_CLK clock period	30	—	—	ns
T_dutycycle	SPIM_CLK duty cycle	45	50	55	%
T_d	Master-in slave-out (MISO) output skew	(2 × T_{spi_ref_clk}) + 3	—	(3 × T_{spi_ref_clk}) + 11	ns
T_su	Master-out slave-in (MOSI) setup time	4	—	—	ns
T_h	Master-out slave-in (MOSI) hold time	9	—	—	ns
T_suss	SPI_SS_N asserted to first SPIM_CLK edge	T_{spi_ref_clk} + 4.2	—	—	ns
T_hss	Last SPIM_CLK edge to SPI_SS_N deasserted	T_{spi_ref_clk} + 4.2	—	—	ns

Figure 6. SPI Slave Output Timing Diagram

Figure 7. SPI Slave Input Timing Diagram

⁸⁸ SPI_SS_N behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.

⁸⁹ The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge.

⁹⁰ Valid values of rx_sample_dly range from 1 to 64 (units are in T_{spi_ref_clk} steps).

HPS SD/MMC Timing Characteristics

Table 81. HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel^® Agilex™ Devices
These timings apply to SD, MMC, and embedded MMC (eMMC) cards operating at 1.8 V.

For specification status, see the Data Sheet Status table
Symbol	Description	Min	Typ	Max	Unit
T_{sdmmc_cclk}	SDMMC_CCLK clock period (Identification mode)	2,500	—	—	ns
	SDMMC_CCLK clock period (SDR12)	40	—	—	ns
	SDMMC_CCLK clock period (SDR25)	20	—	—	ns
T_dutycycle	SDMMC_CCLK duty cycle	45	50	55	%
T_{sdmmc_cclk_jitter}	SDMMC_CCLK output jitter	—	—	2	%
T_{sdmmc_clk}	Internal reference clock before division by 4	5	—	—	ns
T_d	SDMMC_CMD/SDMMC_DATA[7:0] output delay⁹¹	–0.5 + T_{sdmmc_clk} × `drvsel`/2	—	2.5 + (T_{sdmmc_clk} × `drvsel`/2)	ns
T_su	SDMMC_CMD/SDMMC_DATA[7:0] input setup⁹²	6 – (_{Tsdmmc_clk} × `smplsel`/2)	—	—	ns
T_h	SDMMC_CMD/SDMMC_DATA[7:0] input hold⁹²	0.5 + (T_{sdmmc_clk} × `smplsel`/2)	—	—	ns

None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at 1.8 V at power on.

Note: SD cards power up at 3 V. To support SD, your design must include a level shifter between the SD card and the HPS SD/MMC interface.

Figure 8. SD/MMC Timing Diagram

⁹¹ When the drvsel bitfield in the sdmmc register is set to 3 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz for example, the output delay time is 7.5 to 10.5 ns.

⁹² When the smplsel bitfield in the sdmmc register is set to 2 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz for example, the setup time is 1 ns and the hold time is 5.5 ns.

HPS USB UPLI Timing Characteristics

Table 82. HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Min	Typ	Max	Unit
T_{usb_clk}	USB_CLK clock period	—	16.667	—	ns
T_d	Clock to USB_STP/USB_DATA[7:0] output delay	2	—	7	ns
T_su	Setup time for USB_DIR/USB_NXT/USB_DATA[7:0]	4	—	—	ns
T_h	Hold time for USB_DIR/USB_NXT/USB_DATA[7:0]	4	—	—	ns

Figure 9. USB ULPI Timing Diagram

Note: The USB interface supports single data rate (SDR) timing only.

HPS Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 83. Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Min	Typ	Max	Unit
T_clk (1000Base-T)	TX_CLK clock period	—	8	—	ns
T_clk (100Base-T)	TX_CLK clock period	—	40	—	ns
T_clk (10Base-T)	TX_CLK clock period	—	400	—	ns
T_dutycycle (1000Base-T)	TX_CLK duty cycle	45	50	55	%
T_dutycycle (10/100Base-T)	TX_CLK duty cycle	40	50	60	%
T_d ⁹³ ⁹⁴	TXD/TX_CTL to TX_CLK output skew	–0.5	—	0.5	ns

Figure 10. RGMII TX Timing Diagram

Table 84. RGMII RX Timing Requirements for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Min	Typ	Max	Unit
T_clk (1000Base-T)	RX_CLK clock period	—	8	—	ns
T_clk (100Base-T)	RX_CLK clock period	—	40	—	ns
T_clk (10Base-T)	RX_CLK clock period	—	400	—	ns
T_dutycycle (1000Base-T)	RX_CLK duty cycle	45	50	55	%
T_dutycycle (10/100Base-T)	RX_CLK duty cycle	40	50	60	%
T_su	RX_D/RX_CTL to RX_CLK setup time	1	—	—	ns
T_h ⁹⁵	RX_CLK to RX_D/RX_CTL hold time	1	—	—	ns

Figure 11. RGMII RX Timing Diagram

Table 85. Reduced Media Independent Interface (RMII) Clock Timing Requirements for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Min	Typ	Max	Unit
T_clk	REF_CLK clock period, sourced by HPS TX_CLK	—	20	—	ns
T_clk	REF_CLK clock period, sourced by external clock source	—	20	—	ns
T_{dutycycle_int}	Clock duty cycle, REF_CLK sourced by TX_CLK	35	50	65	%
T_{dutycycle_ext}	Clock duty cycle, REF_CLK sourced by external clock source	35	50	65	%

Table 86. RMII TX Timing Requirements for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Min	Typ	Max	Unit
T_d	TX_CLK to TXD/TX_CTL output data delay	2	—	10	ns

Figure 12. RMII TX Timing Diagram

Table 87. RMII RX Timing Requirements for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Min	Typ	Max	Unit
T_su	RX_D/RX_CTL setup time	2	—	—	ns
T_h	RX_D/RX_CTL hold time	1	—	—	ns

Figure 13. RMII RX Timing Diagram

Table 88. Management Data Input/Output (MDIO) Timing Requirements for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Min	Typ	Max	Unit
T_clk	MDC clock period	400	—	—	ns
T_d	MDC to MDIO output data delay	10	—	300	ns
T_su	Setup time for MDIO data	10	—	—	ns
T_h	Hold time for MDIO data	0	—	—	ns

Figure 14. MDIO Timing Diagram

⁹³ Rise and fall times depend on the I/O standard, drive strength, and loading. Intel^® recommends simulating your configuration.

⁹⁴ If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5—2.0 ns with the HPS I/O programmable delay, to meet the PHY's 1-ns data-to-clock skew requirement.

⁹⁵ If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK by 1.5-2 ns, using the HPS I/O programmable delay.

HPS I2C Timing Characteristics

Table 89. HPS I²C Timing Requirements for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Standard Mode		Fast Mode		Unit
Symbol	Description	Min	Max	Min	Max	Unit
T_clk	Serial clock (SCL) clock period	10	—	2.5	—	μs
T_{clk_jitter}	I²C clock output jitter	—	2	—	2	%
T_HIGH ⁹⁶	SCL high period	4⁹⁷	—	0.6⁹⁸	—	μs
T_LOW ⁹⁹	SCL low period	4.7¹⁰⁰	—	1.3¹⁰¹	—	μs
T_SU;DAT	Setup time for serial data line (SDA) data to SCL	0.25	—	0.1	—	μs
T_HD;DAT ¹⁰²	Hold time for SCL to SDA data	0	3.15	0	0.6	μs
T_VD;DAT and T_VD;ACK ¹⁰³	SCL to SDA output data delay	—	3.45¹⁰⁴	—	0.9¹⁰⁵	μs
T_SU;STA	Setup time for a repeated start condition	4.7	—	0.6	—	μs
T_HD;STA	Hold time for a repeated start condition	4	—	0.6	—	μs
T_SU;STO	Setup time for a stop condition	4	—	0.6	—	μs
T_BUF	SDA high pulse duration between STOP and START	4.7	—	1.3	—	μs
T_scl:r ¹⁰⁶	SCL rise time	—	1,000	20	300	ns
T_scl:f ¹⁰⁶	SCL fall time	—	300	6.54	300	ns
T_sda:r ¹⁰⁶	SDA rise time	—	1,000	20	300	ns
T_sda:f ¹⁰⁶	SDA fall time	—	300	6.54	300	ns

Figure 15. I²C Timing Diagram

⁹⁶ You can adjust T_high using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.

⁹⁷ The recommended minimum setting for ic_ss_scl_hcnt is 428. Refer to the SCL_High_time equation in the Intel^® Agilex™ Hard Processor System Technical Reference Manual.

⁹⁸ The recommended minimum setting for ic_fs_scl_hcnt is 75. Refer to the SCL_High_time equation in the Intel^® Agilex™ Hard Processor System Technical Reference Manual.

⁹⁹ You can adjust T_low using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.

¹⁰⁰ The recommended minimum setting for ic_ss_scl_lcnt is 464. Refer to the SCL_Low_time equation in the Intel^® Agilex™ Hard Processor System Technical Reference Manual.

¹⁰¹ The recommended minimum setting for ic_fs_scl_lcnt is 163. Refer to the SCL_Low_time equation in the Intel^® Agilex™ Hard Processor System Technical Reference Manual.

¹⁰² T_HD;DAT is affected by the rise and fall time.

¹⁰³ T_VD;DAT and T_VD;ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).

¹⁰⁴ Use maximum SDA_HOLD = 240 to be within the specification.

¹⁰⁵ Use maximum SDA_HOLD = 60 to be within the specification.

¹⁰⁶ Rise and fall time parameters vary depending on external factors such as the characteristics of the I/O driver, pull-up resistor value, and total capacitance on the transmission line.

HPS NAND Timing Characteristics

Table 90. HPS NAND ONFI 1.0 Timing Requirements for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Min	Max	Unit
T_WP ¹⁰⁷	Write enable pulse width	10	—	ns
T_WH ¹⁰⁷	Write enable hold time	7	—	ns
T_RP ¹⁰⁷	Read enable pulse width	10	—	ns
T_REH ¹⁰⁷	Read enable hold time	7	—	ns
T_CLS ¹⁰⁷	Command latch enable to write enable setup time	10	—	ns
T_CLH ¹⁰⁷	Command latch enable to write enable hold time	5	—	ns
T_CS ¹⁰⁷	Chip enable to write enable setup time	15	—	ns
T_CH ¹⁰⁷	Chip enable to write enable hold time	5	—	ns
T_ALS ¹⁰⁷	Address latch enable to write enable setup time	10	—	ns
T_ALH ¹⁰⁷	Address latch enable to write enable hold time	5	—	ns
T_DS ¹⁰⁷	Data to write enable setup time	7	—	ns
T_DH ¹⁰⁷	Data to write enable hold time	5	—	ns
T_WB ¹⁰⁷	Write enable high to R/B low	—	200	ns
T_CEA	Chip enable to data access time	—	100	ns
T_REA	Read enable to data access time	—	40	ns
T_RHZ	Read enable to data high impedance	—	200	ns
T_RR	Ready to read enable low	20	—	ns

Figure 16. NAND Command Latch Timing Diagram

Figure 17. NAND Address Latch Timing Diagram

Figure 18. NAND Data Output Cycle Timing Diagram

Figure 19. NAND Data Input Cycle Timing Diagram

Figure 20. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle

Figure 21. NAND Read Status Timing Diagram

Figure 22. NAND Read Status Enhanced Timing Diagram

¹⁰⁷ This timing is software programmable. Refer to the NAND Flash Controller chapter in the Intel^® Agilex™ Hard Processor System Technical Reference Manual for more information about software-programmable timing in the NAND flash controller.

HPS Trace Timing Characteristics

Table 91. Trace Timing Requirements for Intel^® Agilex™ Devices
To increase the trace bandwidth, Intel^® recommends routing the trace interface to the FPGA in the HPS Platform Designer component. The FPGA trace interface offers a 64-bit single data rate path that can be converted to double data rate to minimize FPGA I/O usage.

Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed possible. Refer to your trace module data sheet for termination recommendations.

Most trace modules implement programmable clock and data skew, to improve trace data timing margins. Alternatively, you can change the clock-to-data timing relationship with the HPS programmable I/O delay.

For specification status, see the Data Sheet Status table
Symbol	Description	Min	Typ	Max	Unit
T_clk	Trace clock period	6.667	—	—	ns
T_{clk_jitter}	Trace clock output jitter	—	—	2	%
T_dutycycle	Trace clock maximum duty cycle	45	50	55	%
T_d	T_clk to D0–D15 output data delay	–0.5	—	1.3	ns

Figure 23. Trace Timing Diagram

HPS GPIO Interface

The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is 1 debounce clock cycle and the minimum detectable GPIO pulse width is 62.5 µs (at 32 kHz).

If the external signal is driven into the GPIO for less than one clock cycle, the external signal is filtered. If the external signal is between one and two clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If the external signal is more than two clock cycles, the external signal is not filtered.

HPS JTAG Timing Characteristics

Table 92. HPS JTAG Timing Requirements for Intel^® Agilex™ Devices For specification status, see the Data Sheet Status table
Symbol	Description	Min	Typ	Max	Unit
t_JCP	TCK clock period	41.66	—	—	ns
t_JCH	TCK clock high time	20	—	—	ns
t_JCL	TCK clock low time	20	—	—	ns
t_{JPSU (TDI)}	TDI JTAG port setup time	5	—	—	ns
t_{JPSU (TMS)}	TMS JTAG port setup time	5	—	—	ns
t_JPH	JTAG port hold time	0.5	—	—	ns
t_JPCO	JTAG port clock to output	0	—	8	ns
t_JPZX	JTAG port high impedance to valid output	—	—	10	ns
t_JPXZ	JTAG port valid output to high impedance	—	—	10	ns

Figure 24. HPS JTAG Timing Diagram

HPS Programmable I/O Timing Characteristics

Table 93. HPS Programmable I/O Delay (Output Path) for Intel^® Agilex™ Device For specification status, see the Data Sheet Status table
Name	output_val_en	output_val	Description	Min	Typ	Max	Unit
ZERO_CHAIN_DELAY	0	0	Intrinsic I/O delay. Bypasses the delay chain	—	0	—	ps
CHAIN_DELAY	1	0	Intrinsic I/O delay + Minimum + `0` × Chain Delay	—	0	—	ps
ONE_CHAIN_DELAY	1	1	Intrinsic I/O delay + Minimum + 1 × Chain Delay	—	422	—	ps
TWO_CHAIN_DELAY	1	2	Intrinsic I/O delay + Minimum + 2 × Chain Delay	—	518	—	ps
THREE_CHAIN_DELAY	1	3	Intrinsic I/O delay + Minimum + 3 × Chain Delay	—	607	—	ps
FOUR_CHAIN_DELAY	1	4	Intrinsic I/O delay + Minimum + 4 × Chain Delay	—	705	—	ps
FIVE_CHAIN_DELAY	1	5	Intrinsic I/O delay + Minimum + 5 × Chain Delay	—	786	—	ps
SIX_CHAIN_DELAY	1	6	Intrinsic I/O delay + Minimum + 6 × Chain Delay	—	874	—	ps
SEVEN_CHAIN_DELAY	1	7	Intrinsic I/O delay + Minimum + 7 × Chain Delay	—	955	—	ps
EIGHT_CHAIN_DELAY	1	8	Intrinsic I/O delay + Minimum + 8 × Chain Delay	—	1,042	—	ps
NINE_CHAIN_DELAY	1	9	Intrinsic I/O delay + Minimum + 9 × Chain Delay	—	1,126	—	ps
TEN_CHAIN_DELAY	1	10	Intrinsic I/O delay + Minimum + 10 × Chain Delay	—	1,214	—	ps
ELEVEN_CHAIN_DELAY	1	11	Intrinsic I/O delay + Minimum + 11 × Chain Delay	—	1,296	—	ps
TWELVE_CHAIN_DELAY	1	12	Intrinsic I/O delay + Minimum + 12 × Chain Delay	—	1,382	—	ps
THIRTEEN_CHAIN_DELAY	1	13	Intrinsic I/O delay + Minimum + 13 × Chain Delay	—	1,462	—	ps
FOURTEEN_CHAIN_DELAY	1	14	Intrinsic I/O delay + Minimum + 14 × Chain Delay	—	1,552	—	ps
FIFTEEN_CHAIN_DELAY	1	15	Intrinsic I/O delay + Minimum + 15 × Chain Delay	—	1,626	—	ps
—	1	[16:30]	INVALID	—	—	—	—
—	2	—	INVALID	—	—	—	—
—	3	[0:15]	INVALID	—	—	—	—
SIXTEEN_CHAIN_DELAY	3	16	Intrinsic I/O delay + Minimum + 16 × Chain Delay	—	1,798	—	ps
SEVENTEEN_CHAIN_DELAY	3	17	Intrinsic I/O delay + Minimum + 17 × Chain Delay	—	1,885	—	ps
EIGHTEEN_CHAIN_DELAY	3	18	Intrinsic I/O delay + Minimum + 18 × Chain Delay	—	1,967	—	ps
NINETEEN_CHAIN_DELAY	3	19	Intrinsic I/O delay + Minimum + 19 × Chain Delay	—	2,054	—	ps
TWENTY_CHAIN_DELAY	3	20	Intrinsic I/O delay + Minimum + 20 × Chain Delay	—	2,137	—	ps
TWENTYONE_CHAIN_DELAY	3	21	Intrinsic I/O delay + Minimum + 21 × Chain Delay	—	2,222	—	ps
TWENTYTWO_CHAIN_DELAY	3	22	Intrinsic I/O delay + Minimum + 22 × Chain Delay	—	2,305	—	ps
TWENTYTHREE_CHAIN_DELAY	3	23	Intrinsic I/O delay + Minimum + 23 × Chain Delay	—	2,395	—	ps
TWENTYFOUR_CHAIN_DELAY	3	24	Intrinsic I/O delay + Minimum + 24 × Chain Delay	—	2,475	—	ps
TWENTYFIVE_CHAIN_DELAY	3	25	Intrinsic I/O delay + Minimum + 25 × Chain Delay	—	2,564	—	ps
TWENTYSIX_CHAIN_DELAY	3	26	Intrinsic I/O delay + Minimum + 26 × Chain Delay	—	2,644	—	ps
TWENTYSEVEN_CHAIN_DELAY	3	27	Intrinsic I/O delay + Minimum + 27 × Chain Delay	—	2,732	—	ps
TWENTYEIGHT_CHAIN_DELAY	3	28	Intrinsic I/O delay + Minimum + 28 × Chain Delay	—	2,808	—	ps
TWENTYNINE_CHAIN_DELAY	3	29	Intrinsic I/O delay + Minimum + 29 × Chain Delay	—	2,901	—	ps
THIRTY_CHAIN_DELAY	3	30	Intrinsic I/O delay + Minimum + 30 × Chain Delay	—	2,979	—	ps

Table 94. HPS Programmable I/O Delay (Input Path) for Intel^® Agilex™ Device For specification status, see the Data Sheet Status table
Name	input_val_en	input_val	Description	Min	Typ	Max	Unit
ZERO_CHAIN_DELAY	0	0	Intrinsic I/O delay. Bypasses the delay chain	—	0	—	ps
CHAIN_DELAY	1	0	Intrinsic I/O delay + Minimum + `0` × Chain Delay	—	0	—	ps
ONE_CHAIN_DELAY	1	1	Intrinsic I/O delay + Minimum + 1 × Chain Delay	—	422	—	ps
TWO_CHAIN_DELAY	1	2	Intrinsic I/O delay + Minimum + 2 × Chain Delay	—	518	—	ps
THREE_CHAIN_DELAY	1	3	Intrinsic I/O delay + Minimum + 3 × Chain Delay	—	607	—	ps
FOUR_CHAIN_DELAY	1	4	Intrinsic I/O delay + Minimum + 4 × Chain Delay	—	705	—	ps
FIVE_CHAIN_DELAY	1	5	Intrinsic I/O delay + Minimum + 5 × Chain Delay	—	786	—	ps
SIX_CHAIN_DELAY	1	6	Intrinsic I/O delay + Minimum + 6 × Chain Delay	—	874	—	ps
SEVEN_CHAIN_DELAY	1	7	Intrinsic I/O delay + Minimum + 7 × Chain Delay	—	955	—	ps
EIGHT_CHAIN_DELAY	1	8	Intrinsic I/O delay + Minimum + 8 × Chain Delay	—	1,042	—	ps
NINE_CHAIN_DELAY	1	9	Intrinsic I/O delay + Minimum + 9 × Chain Delay	—	1,126	—	ps
TEN_CHAIN_DELAY	1	10	Intrinsic I/O delay + Minimum + 10 × Chain Delay	—	1,214	—	ps
ELEVEN_CHAIN_DELAY	1	11	Intrinsic I/O delay + Minimum + 11 × Chain Delay	—	1,296	—	ps
TWELVE_CHAIN_DELAY	1	12	Intrinsic I/O delay + Minimum + 12 × Chain Delay	—	1,382	—	ps
THIRTEEN_CHAIN_DELAY	1	13	Intrinsic I/O delay + Minimum + 13 × Chain Delay	—	1,462	—	ps
FOURTEEN_CHAIN_DELAY	1	14	Intrinsic I/O delay + Minimum + 14 × Chain Delay	—	1,552	—	ps
FIFTEEN_CHAIN_DELAY	1	15	Intrinsic I/O delay + Minimum + 15 × Chain Delay	—	1,626	—	ps
—	1	[16:30]	INVALID	—	—	—	—
—	2	—	INVALID	—	—	—	—
—	3	[0:15]	INVALID	—	—	—	—
SIXTEEN_CHAIN_DELAY	3	16	Intrinsic I/O delay + Minimum + 16 × Chain Delay	—	1,798	—	ps
SEVENTEEN_CHAIN_DELAY	3	17	Intrinsic I/O delay + Minimum + 17 × Chain Delay	—	1,885	—	ps
EIGHTEEN_CHAIN_DELAY	3	18	Intrinsic I/O delay + Minimum + 18 × Chain Delay	—	1,967	—	ps
NINETEEN_CHAIN_DELAY	3	19	Intrinsic I/O delay + Minimum + 19 × Chain Delay	—	2,054	—	ps
TWENTY_CHAIN_DELAY	3	20	Intrinsic I/O delay + Minimum + 20 × Chain Delay	—	2,137	—	ps
TWENTYONE_CHAIN_DELAY	3	21	Intrinsic I/O delay + Minimum + 21 × Chain Delay	—	2,222	—	ps
TWENTYTWO_CHAIN_DELAY	3