AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

ID 683049
Date 12/19/2017

Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

This application note showcases the synchronization of two ×8-lane Intel® Stratix® 10 FPGA JESD204B RX IP cores to interoperate with the 12-bit, 16-lane Texas Instruments (TI) ADC12DJ3200 Evaluation Module (EVM) running at 6.4 gigabits per second (Gbps) per lane connected through FMC+ port A connector.

TI wideband ADC12DJ3200 device is the 12-bit converter which is capable of operating at up to 3.2 gigasamples per second (Gsps) in dual channel mode or 6.4 Gsps in an interleaved single channel mode. This design is programmed to run at the fastest sample rate of 6.4 Gsps in single channel mode, where this mode effectively interleaves the two analog-to-digital converter (ADC) channels together to form a single channel ADC at twice the sampling rate.

Applications such as high-density phased array radar, satellite communications, 5G systems, and medical imaging are driving the need for increased data throughput, higher bandwidth, and lower power. Small package size and lower PCB cost are preferred in these applications.