AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

ID 683049
Date 12/19/2017

Key Features

This reference design provides the following key features:

  • Two 8-lane simplex RX JESD204B IP cores interoperate with the ADC12DJ3200 EVM through the Intel® Stratix® 10 Transceiver Signal Integrity Development Kit FMC+ port A running at 6.4 Gbps per lane. The JESD204B IP core has the following parameters:
    • L=8
    • M=8
    • F=8
    • S=5
    • N=12
    • N’=12
    • K=4
    • HD=0
    • SCR=1
    • CS=CF=0
  • The LMK04828 clock generator on the ADC12DJ3200 EVM provides 160 MHz for I/O PLL core reference clock and 160 MHz for transceiver CDR reference clock. These clocks are transmitted from a single clock chip through the FMC+ port A to the core reference clock pin and the dedicated transceiver pin at the FPGA. The LMK04828 also provides a clock to LMX2582, where the LMX2582 synthesizer generates a 3,200 MHz ADC sampling clock.
  • The I/O PLL on the FPGA generates link clock and frame clock. The IP cores, RX transport layers, and deterministic latency measurement block are sourced from link clock. The frame clock is supplied to RX transport layers, test pattern checkers, and any application layer.
  • The LMK04828 clock chip generates continuous SYSREF signal for the RX JESD204B IP cores at the FPGA and the ADC12DJ3200 device.
  • The deterministic latency measurement block measures the number of link clock counts between the start of combined SYNC_N deassertion output from the two JESD204B IP cores to the first user data output to ensure latency is deterministic.
  • Frequency Checker monitors to ensure the I/O PLL core reference clock and transceiver CDR reference clock from the EVM clock generator and RX recovered clock frequency generated from CDR are correct.
  • The main.tcl script (located at the <project directory>/system_console directory) generated from the JESD204B Example Design (LMF=888, 6.144 Gbps) (Stratix 10 only) preset is enhanced to support multi-link design. Refer to the Procedures in the main.tcl System Console Script table for details about the .tcl procedures.
  • A Signal Tap II file is included in this design for debug assistance, such as monitoring the short transport pattern at RX transport layers, checking correct octet ramp pattern at the output of the JESD204B IP cores, and checking the output counter to ensure design is deterministic from one power cycle to another.