AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

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ID 683049
Date 12/19/2017
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design x
Reference Design Block Diagram Key Features Submodules in the Top-Level HDL Files Requirements Reference Design Walkthrough Procedures in the main.tcl System Console Script Document Revision History for AN 833: Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Requirements x
Hardware Requirements Software Requirements
Reference Design Walkthrough x
Hardware Set Up Running the Reference Design Viewing the Results Rebuilding Design
Running the Reference Design x
Compiling the Project to Include Signal Tap II File Setting Up the TI ADC12DJxx00 GUI Software and Board Configuring the FPGA Checking the Basic Operation Executing the .tcl Code and Initializing the JESD204B Links Checking the Deterministic Latency
Viewing the Results x
Link Up Test Results Short Transport Layer and Ramp Test Mode Test Results Deterministic Latency Test Results
Short Transport Layer and Ramp Test Mode Test Results x
Verifying Short Transport Test Patterns at Receiver Transport Layer Verifying Ramp Pattern at Output Data of DLL to the Input Receiver Transport Layer
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

Procedures in the main.tcl System Console Script

Table 4.  Procedures in the main.tcl System Console Script
Procedure Value Description
start_basic_test — Main procedure that performs global reset, set checker test mode, enable SYSREF continuous detection mode, clear JESD204B IP cores error status registers, and report link status.
reset — Perform global reset.
force_link_frame_reset 0, 1

0: Deassert link and frame reset.

1: Assert and hold link and frame reset.

Note: Link and frame clock domains should be held in reset while writing to the JESD204B IP control and status register (CSR).
set_testmode alt, ramp, prbs

alt: Set pattern checker to alternate pattern.

ramp: Set pattern checker to ramp pattern.

prbs: Set pattern checker to pseudo-random binary sequence (PRBS) pattern.

sysref_con — Enable SYSREF continuous detection with SYSREF single detection.
rbd_offset integer Adjust RBD offset value to eliminate RX lane deskew error if needed. Refer to the JESD204B IP Core User Guide for more details.
read_status_pio —

Read the status of the parallel I/O (PIO) registers. The PIO status has the following configurations:

  • Bit 0—Core PLL locked
  • Bit 1—RX transceiver ready (Link 0)
  • Bit 2—RX link error (Link 0)
  • Bit 3—RX transceiver ready (Link 1)
  • Bit 4—RX link error (Link 1)
Note: Use the read_err_status procedure to report error in description.
read_err_status — Read the JESD204B IP error status registers. For detailed description of the status registers, refer to the Addressmap Information for 'altera_jesd204_rx_regmap'.
clear_err_status — Clear the JESD204B IP error status registers.
read_rx_status0 — Read JESD204B IP rx_status0 register. For detailed description of the status registers, refer to the Addressmap Information for 'altera_jesd204_rx_regmap'.
wait_seconds integer Set to wait for integer seconds.
eval_test — Report the link status.
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