AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

ID 683049
Date 12/19/2017

Compiling the Project to Include Signal Tap II File

The reference design provided does not enable Signal Tap II Logic Analyzer in the Intel® Quartus® Prime project.

To compile the design that include the Signal Tap II file (.stp) into the Intel® Quartus® Prime project, follow these steps:

  1. To test the reference design targeted for Intel® Stratix® 10 GX device, download the reference design file to your local project directory.
  2. Launch the Intel® Quartus® Prime Pro Edition software.
  3. To prepare the design template in the Intel® Quartus® Prime Pro Edition software GUI, click File > Open and change the file type to the Quartus Prime Design Template File (*.par). Browse to the <project>.par file and click Ok.
  4. Turn on Assignments > Settings > Category > Enable Signal Tap II Logic Analyzer.
  5. Browse to the stp1.stp file located at the /stp directory and click Ok.
  6. To compile the project, select Processing > Start Compilation.